參數(shù)資料
型號(hào): AD7143ACPZ-1REEL
廠商: Analog Devices Inc
文件頁(yè)數(shù): 9/57頁(yè)
文件大?。?/td> 0K
描述: IC CONV CAP-TO-DGTL PROG 16LFCSP
標(biāo)準(zhǔn)包裝: 5,000
類型: 電容數(shù)字轉(zhuǎn)換器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 1mA
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 帶卷 (TR)
AD7143
Rev. 0 | Page 16 of 56
Low Power Mode CDC Conversion Sequence Time
with Delay
The frequency of each CDC conversion while operating in the
low power automatic wake-up mode is controlled by using the
LP_CONV_DELAY register located at Address 0x000[3:2], in
addition to the registers listed in Table 8.
This feature provides some flexibility for optimizing the
conversion time to meet system requirements vs. AD7143
power consumption. For example, maximum power savings is
achieved when the LP_CONV_DELAY register is set to 3. With
a setting of 3, the AD7143 automatically wakes up, performing a
conversion every 800 ms.
Table 9. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits
Delay Between Conversions
00
200 ms
01
400 ms
10
600 ms
11
800 ms
Figure 26 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC
conversion time is set by tCONV_FP and the LP_CONV_DELAY
register.
CONVERSION
SEQUENCE N
CONVERSION
SEQUENCE N + 1
CDC
CONVERSION
LP_CONV_DELAY
tCONV_LP
tCONV_FP
06
47
2-
0
24
Figure 26. Low Power Mode CDC Conversion Sequence Time
CDC CONVERSION RESULTS
Certain high-resolution sensors require the host to read back
the CDC conversion results for processing. The registers
required for host processing are located in the Bank 3 registers.
The host processes the data readback from these registers using
a software algorithm to determine position information. In
addition to the results registers in the Bank 3 registers, the
AD7143 provides the 16-bit CDC output data directly starting
at Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.
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