參數(shù)資料
型號： AD7143ACPZ-1REEL
廠商： Analog Devices Inc
文件頁數(shù)： 25/57頁
文件大?。?/td> 0K
描述： IC CONV CAP-TO-DGTL PROG 16LFCSP
標準包裝： 5,000
類型： 電容數(shù)字轉換器
輸入類型： 邏輯
輸出類型： 邏輯
接口： I²C
電流 - 電源： 1mA
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤，CSP
供應商設備封裝： 16-LFCSP-VQ
包裝： 帶卷 (TR)
AD7143
Rev. 0 | Page 30 of 56
SDA
DEV
A6
DEV
A5
DEV
A4
R/W
A7
A6
SCLK
DEV
A3
A1
A0
1
26
234
17
18
19
20
25
DEV
A2
DEV
A1
DEV
A0
ACK
A15
A14
11
16
5678
910
AD7143 DEVICE ADDRESS
A9
A8
REGISTER ADDRESS [A15:A8]
REGISTER ADDRESS [A7:A0]
ACK
35
28
30
34
37
36
44
38
45
D1
D0
D7
D6
SR
ACK
46
P
DEV
A6
DEV
A5
DEV
A4
12
3
t8
t7
t6
t5
t4
t2
t1
t3
AD7143 DEVICE ADDRESS
ACK
27
AD7143 DEVICE ADDRESS
DEV
A6
DEV
A5
DEV
A1
DEV
A0
R/W
29
39
35
28
30
34
37
36
44
38
45
D1
D0
D7
D6
S
ACK
46
P
t5
t4
AD7143 DEVICE ADDRESS
DEV
A6
DEV
A5
DEV
A1
DEV
A0
R/W
29
39
P
USING
REPEATED START
SEPARATE READ AND
WRITE TRANSACTIONS
ACK
START
REGISTER DATA [D7:D0]
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 1 0].
5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB Xs ARE DON’T CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY LOW ACK BITS.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
0
6472-
037
Figure 40. Example of I2C Timing for Single Register Readback Operation
ACK
WRITE
OUTPUT FROM MASTER
S
P
ACK
ACK = NO ACKNOWLEDGE BIT
ACK
W
ACK
READ (USING REPEATED START)
S
ACK
W
ACK
R
SR
P
ACK
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)
S
ACK
W
ACK
R
P
S
ACK
OUTPUT FROM AD7143
S = START BIT
P = STOP BIT
SR = REPEATED START BIT
ACK = ACKNOWLEDGE BIT
7-BIT DEVICE
ADDRESS
REGISTER ADDR
[15:8]
REGISTER ADDR
[7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
6-BIT DEVICE
ADDRESS
REGISTER ADDR
LOW BYTE
REGISTER ADDR
HIGH BYTE
7-BIT DEVICE
ADDRESS
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
6-BIT DEVICE
ADDRESS
REGISTER ADDR
LOW BYTE
REGISTER ADDR
HIGH BYTE
7-BIT DEVICE
ADDRESS
0
6472-
038
Figure 41. Example of Sequential I2C Write and Readback Operation
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