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| 型號： | AD7143ACPZ-1REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV CAP-TO-DGTL PROG 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | 電容數(shù)字轉(zhuǎn)換器 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | I²C |
| 電流 - 電源： | 1mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
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AD7143
Rev. 0 | Page 19 of 56
CALIBRATION ENABLED
tRECAL_TIMEOUT
16
30
70
tCONV_FP
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
RECALIBRATION TIMEOUT
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CDC CONVERSION
SEQUENCE
(INTERNAL)
RECALIBRATION
(INTERNAL)
USER APPROACHES
SENSOR HERE
USER LEAVES SENSOR
AREA HERE
tCALDIS
tRECAL
CALIBRATION DISABLED
NOTES
1. SEQUENCE CONVERSION TIME
tCONV_LP = tCONV_FP + LP_CONV_DELAY.
2.
tCALDIS = tCONV_LP × LP_PROXIMITY_CNT × 4.
3.
tRECAL_TIMEOUT = tCONV_FP × LP_PROXIMITY_RECAL.
4.
tRECAL = 2 × tCONV_LP.
06
47
2-
02
8
Figure 30. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMIT_CNT = 4 and LP_PROXIMITY_RECAL = 10
FF_SKIP_CNT
The proximity detection fast FIFO is used by the on-chip logic
to determine if proximity is detected. The fast FIFO expects to
receive samples from the converter at a set rate. Using
FF_SKIP_CNT normalizes the frequency of the samples going
into the FIFO, regardless of how many conversion stages are in a
sequence. In Register 0x02, Bits[3:0] are the fast filter skip control,
FF_SKIP_CNT. This value determines which CDC samples are not
used (skipped) in the proximity detection fast FIFO.
Determining the FF_SKIP_CNT value is required only once
during the initial setup of the capacitance sensor interface.
Table 11 shows how FF_SKIP_CNT controls the update rate to
the fast FIFO. The recommended value for FF_SKIP_CNT
when using all 12 conversion stages on the AD7143 is
FF_SKIP_CNT = 0000 = no samples skipped
SLOW FIFO
As shown in Figure 31, a number of FIFOs are implemented on
the AD7143. These FIFOs are located in Bank 3 of the on-chip
memory. The slow FIFOs are used by the on-chip logic to
monitor the ambient capacitance level from each sensor.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12] are the slow FIFO skip control for
full power mode, AVG_FP_SKIP. Bits[15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP. These values determine which CDC samples
are not used (skipped) in the slow FIFO. Changing theses values
slows down or speeds up the rate at which the ambient
capacitance value tracks the measured capacitance value read by
the converter.
Slow FIFO update rate in full power mode is equal to
AVG_FP_SKIP × [(3 × Decimation Rate) ×
(SEQUENCE_STAGE_NUM +1) × (FF_SKIP_CNT +1) × 4 × 10-7]
Slow FIFO update rate in low power mode is equal to
(AVG_LP_SKIP +1) × [(3 × Decimation Rate) ×
SEQUENCE_STAGE_NUM +1) × (FF_SKIP_CNT +1) × 4 × 10-7] /
[(FF_SKIP_CNT +1)+ LP_CONV_DELAY]
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples
from the converter at a rate of 33 ms to 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many
conversion stages are in a sequence.
Determining the AVG_FP_SKIP and AVG_LP_SKIP value is
only required once during the initial setup of the capacitance
sensor interface. Recommended values for these settings when
using all 12 conversion stages on the AD7143 are
AVG_FP_SKIP = 00 = skip 3 samples
AVG_LP_SKIP = 00 = no samples skipped
SLOW_FILTER_UPDATE_LVL
The SLOW_FILTER_UPDATE_LVL controls whether or not
the most recent CDC measurement goes into the slow FIFO
(slow filter). The slow filter is updated when the difference
between the current CDC value and last value pushed into the
slow FIFO is greater than SLOW_FILTER_UPDATE_LVL. This
variable is in Ambient Control Register 1, at Address 0x003.
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