The AD7143 is available with a fixed address I2
參數(shù)資料
型號(hào)： AD7143ACPZ-1REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/57頁(yè)
文件大小： 0K
描述： IC CONV CAP-TO-DGTL PROG 16LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類(lèi)型： 電容數(shù)字轉(zhuǎn)換器
輸入類(lèi)型： 邏輯
輸出類(lèi)型： 邏輯
接口： I²C
電流 - 電源： 1mA
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP-VQ
包裝： 帶卷 (TR)
AD7143
Rev. 0 | Page 28 of 56
SERIAL INTERFACE
The AD7143 is available with a fixed address I2C-compatible
interface.
I2C COMPATIBLE INTERFACE
The AD7143 supports the industry standard 2-wire I2C serial
interface protocol. The two wires associated with the I2C timing are
the SCLK and the SDA inputs. The SDA is an I/O pin that allows
both register write and register readback operations. The AD7143 is
always a slave device on the I2C serial interface bus.
The AD7143 has a single fixed 7-bit device address,
Address 0101 110. The AD7143 responds when the master
device sends its device address over the bus. The AD7143
cannot initiate data transfers on the bus.
Table 14. AD7143 I2C Fixed Device Address
DEV
A6
DEV
A5
DEV
A4
DEV
A3
DEV
A2
DEV
A1
DEV
A0
0
1
0
1
0
Data Transfer
Data is transferred over the I2C serial interface in 8-bit bytes.
The master initiates a data transfer by establishing a start con-
dition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCLK, remains high. This
indicates that an address/data stream follows.
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus an R/W bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus now remain idle
while the selected device waits for data to be read from, or
written to it. If the R/W bit is a 0, the master writes to the slave
device. If the R/W bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period, since a low-to-high transition when the clock is
high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCLK remains high. If the AD7143
encounters a stop condition, it returns to its idle condition, and
the address pointer register resets to Address 0x00.
SDA
DEV
A6
DEV
A5
DEV
A4
R/W
A7
A6
SCLK
DEV
A3
A1
A0
1
26
23
4
17
18
19
20
25
DEV
A2
DEV
A1
DEV
A0
ACK
A15
A14
11
16
5
678
910
START
AD7143 DEVICE ADDRESS
A9
A8
REGISTER ADDRESS [A15:A8]
REGISTER ADDRESS [A7:A0]
ACK
D15
D14
D9
D8
35
27
28
29
34
37
36
43
38
44
D1
D0
D7
D6
ACK
45
46
ACK
STOP
DEV
A6
DEV
A5
DEV
A4
12
3
START
t8
t7
t6
t5
t4
t2
t1
t3
AD7143 DEVICE ADDRESS
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 1 0].
4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X ARE DON’T CARE BITS.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
REGISTER DATA [D15:D8]
REGISTER DATA [D7:D0]
0
64
72
-03
6
Figure 39. Example of I2C Timing for Single Register Write Operation
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