參數(shù)資料
型號： AD7143ACPZ-1REEL
廠商： Analog Devices Inc
文件頁數(shù)： 29/57頁
文件大小： 0K
描述： IC CONV CAP-TO-DGTL PROG 16LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類型： 電容數(shù)字轉(zhuǎn)換器
輸入類型： 邏輯
輸出類型： 邏輯
接口： I²C
電流 - 電源： 1mA
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP-VQ
包裝： 帶卷 (TR)
AD7143
Rev. 0 | Page 34 of 56
REGISTER MAP
The AD7143 address space is divided into three different
register banks, referred to as Bank 1, Bank 2, and Bank 3.
Figure 47 illustrates the division of these three banks.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Bank 2 registers contain the configuration registers used for
uniquely configuring the CIN inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
Bank 3 registers contains the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7143 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power up and configuration of the Bank 2
registers.
REGISTER BANK 1
ADDR 0x000
ADDR 0x018
ADDR 0x001
ADDR 0x005
ADDR 0x008
ADDR 0x00B
ADDR 0x017
ADDR 0x013
ADDR 0x7F0
REGISTER BANK 2
ADDR 0x080
ADDR 0x0B8
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
REGISTER BANK 3
ADDR 0x0E0
ADDR 0x0B8
ADDR 0x088
ADDR 0x090
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x0B0
ADDR 0x042
ADDR 0x043
INVALID DO NOT ACCESS
24
REG
IST
ERS
PROXIMITY STATUS REGISTER
INVALID DO NOT ACCESS
DEVICE ID REGISTER
CDC 16-BIT CONVERSION DATA
(8 REGISTERS)
INTERRUPT STATUS
(3 REGISTERS)
INTERRUPT ENABLE
(3 REGISTERS)
CALIBRATION AND SET UP
(4 REGISTERS)
SET UP CONTROL
(1 REGISTER)
64
R
E
G
IS
T
E
R
S
28
8REG
IST
ERS
STAGE7 CONFIGURATION
(8 REGISTERS)
STAGE6 CONFIGURATION
(8 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
STAGE3 CONFIGURATION
(8 REGISTERS)
STAGE2 CONFIGURATION
(8 REGISTERS)
STAGE1 CONFIGURATION
(8 REGISTERS)
STAGE0 CONFIGURATION
(8 REGISTERS)
STAGE7 RESULTS
(36 REGISTERS)
STAGE6 RESULTS
(36 REGISTERS)
STAGE5 RESULTS
(36 REGISTERS)
STAGE4 RESULTS
(36 REGISTERS)
STAGE3 RESULTS
(36 REGISTERS)
STAGE2 RESULTS
(36 REGISTERS)
STAGE1 RESULTS
(36 REGISTERS)
STAGE0 RESULTS
(36 REGISTERS)
UNUSED (4 REGISTERS)
0
6472
-0
44
Figure 47. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers
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