參數(shù)資料
型號(hào): AD7143ACPZ-1REEL
廠商: Analog Devices Inc
文件頁數(shù): 21/57頁
文件大?。?/td> 0K
描述: IC CONV CAP-TO-DGTL PROG 16LFCSP
標(biāo)準(zhǔn)包裝: 5,000
類型: 電容數(shù)字轉(zhuǎn)換器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 1mA
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 帶卷 (TR)
AD7143
Rev. 0 | Page 27 of 56
Table 13. Interrupt Mode Registers
Interrupt Mode
Interrupt Enable
Register Address
Interrupt Status
Register Address
Notes
Sensor Touch
Interrupt asserted when the user contacts a sensor.
See Figure 37.
Low
0x005
0x008
Enable for the CIN inputs connected to the CDC
positive stage.
High
0x006
0x009
Enable for the CIN inputs connected to the CDC
negative stage.
CDC Conversion Complete
0x007
0x00A
Continuous interrupt at the end of each STAGEx that
is enabled.
2
1
CONVERSIONS
SERIAL
READS
STAGE0 STAGE1 STAGE2 STAGE3
STAGE4 STAGE5 STAGE6 STAGE7
STAGE8 STAGE9 STAGE10 STAGE11 STAGE0 STAGE1
NOTES
1. THIS IS AN EXAMPLE OF A CDC CONVERSION COMPLETE INTERRUPT.
2. THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED
AT THE END OF A CONVERSION CYCLE FOR STAGE0 ONLY.
3. STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9)
STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0
STAGEx_COMPLETE_EN (ADDRESS 0x007) = 1
INT
06
47
2-
03
5
Figure 38. Example of Configuring the Registers for End of Conversion Interrupt Setup
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