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參數(shù)資料
| 型號： | AD7143ACPZ-1REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV CAP-TO-DGTL PROG 16LFCSP |
| 標準包裝： | 5,000 |
| 類型： | 電容數(shù)字轉換器 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | I²C |
| 電流 - 電源： | 1mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
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AD7143
Rev. 0 | Page 29 of 56
Writing Data over the I2C Bus
The process for writing to the AD7143 over the I2C bus is
shown in Figure 39 and Figure 41. The device address is sent
over the bus followed by the R/W bit set to 0. This is followed
by two bytes of data that contain the 10-bit address of the
internal data register to be written. The following bit map shows
the upper register address bytes. Note that Bit 7 to Bit 2 in the
upper address byte are don’t care bits. The address is contained
in the 10 LSBs of the register address bytes.
MSB
LSB
7
6
5
4
3
2
1
0
X
Register
Address
Bit 9
Register
Address
Bit 8
The following bit map shows the lower register address bytes.
MSB
LSB
7
6
5
4
3
2
1
0
Reg.
Addr.
Reg.
Addr.
Reg.
Addr.
Reg.
Addr.
Reg.
Addr.
Reg.
Addr.
Reg.
Addr.
Reg.
Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The third data byte contains the 8 MSBs of the data to be
written to the internal register. The fourth data byte contains
the 8 LSBs of data to be written to the internal register.
The AD7143 address pointer register automatically increments
after each write. This allows the master to sequentially write to all
registers on the AD7143 in the same write transaction. However,
the address pointer register does not wrap around after the last
address.
Any data written to the AD7143 after the address pointer has
reached its maximum value is discarded.
All registers on the AD7143 are 16-bit. Two consecutive 8-bit
data bytes are combined and written to the 16-bit registers. To
avoid errors, all writes to the device must contain an even
number of data bytes.
To finish the transaction, the master generates a stop condition
on SDA, or generates a repeat start condition if the master is to
maintain control of the bus.
Reading Data over the I2C Bus
To read from the AD7143, the address pointer register must first
be set to the address of the required internal register. The master
performs a write transaction, and writes to the AD7143 to set the
address pointer. The master then outputs a repeat start condition
to keep control of the bus, or, if this is not possible, ends the write
transaction with a stop condition. A read transaction is initiated,
with the R/W bit set to 1.
The AD7143 supplies the upper eight bits of data from the
addressed register in the first readback byte, followed by the
lower eight bits in the next byte. This is shown in Figure 40 and
Figure 41.
Because the address pointer automatically increases after each
read, the AD7143 continues to output readback data until the
master puts a no acknowledge and stop condition on the bus. If
the address pointer reaches its maximum value, and the master
continues to read from the part, the AD7143 repeatedly sends
data from the last register addressed.
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