參數(shù)資料
型號(hào)： AD7143ACPZ-1REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/57頁(yè)
文件大小： 0K
描述： IC CONV CAP-TO-DGTL PROG 16LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類型： 電容數(shù)字轉(zhuǎn)換器
輸入類型： 邏輯
輸出類型： 邏輯
接口： I²C
電流 - 電源： 1mA
安裝類型： 表面貼裝
封裝/外殼： 16-VQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP-VQ
包裝： 帶卷 (TR)
AD7143
Rev. 0 | Page 26 of 56
INTERRUPT OUTPUT
The AD7143 has an interrupt output that triggers an interrupt
service routine on the host processor. The INT signal is on
Pin 14, and is an open-drain output. There are two types of
interrupt events on the AD7143: a CDC conversion complete
interrupt and a sensor touch interrupt. Each interrupt has
enable and status registers described in Table 13. The
conversion complete and sensor threshold interrupts can be
enabled on a per conversion stage basis. The status registers
indicate what type of interrupt triggered the INT pin. Status
registers are cleared, and the INT signal is reset high, during a
read operation of the interrupt status registers. The signal
returns high as soon as the read address has been set up.
CDC CONVERSION COMPLETE INTERRUPT
The AD7143 interrupt signal asserts low to indicate the
completion of a conversion stage, and new conversion result
data is available in the registers.
The interrupt can be independently enabled for each conversion
stage. Each conversion stage complete interrupt can be enabled
via the STAGE_COMPLETE_EN register (Address 0x007). This
register has a bit that corresponds to each conversion stage.
Setting this bit to 1 enables the interrupt for that stage. Clearing
this bit to 0 disables the conversion complete interrupt for that
stage. Figure 38 shows an end of conversion interrupt timing
with the STAGE0 interrupt enabled.
In normal operation, the AD7143’s interrupt is enabled only for
the last stage in a conversion sequence as shown in Figure 38.
Register 0x00A is the conversion complete interrupt status
register. Each bit in this register corresponds to a conversion
stage. If a bit is set, it means that the conversion complete
interrupt for the corresponding stage was triggered. This
register is cleared on a read, provided the underlying condition
that triggered the interrupt has gone away.
SENSOR TOUCH INTERRUPT
The sensor touch interrupt mode is implemented when the host
processor requires an interrupt only when a sensor is contacted.
Configuring the AD7143 into this mode results in the interrupt
being asserted when the user makes contact with the sensor and
again when the user lifts off the sensor. The second interrupt is
required to alert the host processor that the user is no longer
contacting the sensor.
The registers located at Address 0x005 and Address 0x006 are
used to enable the interrupt output for each stage. The registers
located at Address 0x008 and Address 0x009 are used to read
back the interrupt status for each stage.
Figure 37 shows the interrupt output timing during contact with
one of the sensors connected to STAGE0 while operating in the
sensor touch interrupt mode. For a low limit configuration, the
interrupt output is asserted as soon as the sensor is contacted and
again after the user has stopped contacting the sensor.
Note that the interrupt output remains low until the host
processor reads back the interrupt status registers located at
Address 0x008 and Address 0x009.
The interrupt output is asserted when there is a change in the
threshold status bits. This could indicate that a user is now
touching the sensor(s) for the first time, the number of sensors
being touched has changed, or the user is no longer touching
the sensor(s). Reading the status bits in the interrupt status
register shows the current sensor activations.
4
2
CONVERSION
STAGE
SERIAL
READ BACK
INT OUTPUT
3
1
STAGE1
STAGE0
FINGER ON SENSOR
FINGER OFF SENSOR
1USER TOUCHING DOWN ON SENSOR.
2ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT.
3USER LIFTING OFF OF SENSOR.
4ADDRESS 0x008 READ BACK TO CLEAR INTERRUPT.
06
47
2-
0
34
Figure 37. Example of Sensor Touch Interrupt
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