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型號(hào)：	935274744557
廠商：	NXP SEMICONDUCTORS
元件分類：	消費(fèi)家電
英文描述：	SPECIALTY CONSUMER CIRCUIT, PBGA456
封裝：	27 X 27 MM, 1.75 MM HIEGHT, PLASTIC, MS-034, BGA-456
文件頁(yè)數(shù)：	820/828頁(yè)
文件大?。?/td>	7748K
代理商：	935274744557

Philips Semiconductors

PNX15xx Series

Volume 1 of 1

Chapter 2: Overview

PNX15XX_SER_3

Product data sheet

Rev. 3 — 17 March 2006

PNX15xx Series provides 5 chip selects for the XIO bus. The TM3260 can execute or

read from direct addressable Flash types. Execution from Flash is low performance,

and only recommended for boot usage. After boot, it is recommended that code les

be transferred from Flash to DRAM where they can be executed more efciently.

Flash cannot be the target of a module DMA write, because write operations require

a software ash programming protocol.

Execution and direct addressed read operations only apply to addressable Flash

types, such as traditional Flash, and not to the “l(fā)e system like” NAND Flash type.

Peak page mode read performance is 66 MB/s for 16-bit devices and 33 MB/s for 8-

bit devices such as the congurable x8/x16 Intel StrataFlash (28FxxxJ3A, 32Mbits,

64Mbits, 128Mbits) and ST MLC-NOR ash (M58LW064A, 64Mbits). Cross-page

random read accesses each take 4 to 5 PCI clock cycles depending on the access-

time of the device.

Flash is mostly used during system boot or low bandwidth system operation to

provide a small, non-volatile le system.

TM3260 VLIW Media Processor Core

The TM3260 CPU is a version of the TriMedia 32-bit VLIW media processor. This

Very Long Instruction Word (VLIW) processor operates at up to 300 MHz with 5

instructions per clock cycle, and provides an extensive set of multimedia instructions.

It implements the TriMedia PNX1300 Series instruction set, and has a superset of the

PNX1300 Series functional units as well as a superset of the multimedia instruction

set for better t with MPEG-4 advanced prole decoding. It is backwards compatible

with PNX1300 Series CPU, but has a larger Instruction cache (also referred as I$ or

Icache) for improved performance. In addition, re-compilation of source code results

in higher media performance due to the additional functional units.

The TM3260 supports 32-bit integer and IEEE compatible 32-bit oating point data

formats. It also provides a Single Instruction Multiple Data (SIMD) style operation set

for operating on dual 16-bit or quad 8-bit packed data.

At 266 MHz it has a peak oating point compute capacity of 1.0 Goperations/s,

and has 1.3 Gmultiply-add/s capability on 16-bit data. Its dual access 16 KB 8-

way set-associative data cache provides a CPU local data bandwidth of 2.0 GB/s.

Its 64 KB 8-way set-associative instruction cache provides 224 bits of instructions

every clock cycle (7.1 GB/s), for an instruction rate of 8.8 Gop/s.

At 300 MHz it has a peak oating point compute capacity of 1.4 Goperations/s,

and has 1.5 Gmultiply-add/s capability on 16-bit data. Its dual access 16 KB 8-

way set-associative data cache provides a CPU local data bandwidth of 2.3 GB/s.

Its 64 KB 8-way set-associative instruction cache provides 224 bits of instructions

every clock cycle (8.0 GB/s), for an instruction rate of 9.9 GB/s.

The TM3260 has sufcient compute performance to deal with a variety of future

operating modes. By itself, the processor can decode any known compressed video

stream and associated audio at full frame rate, such as decoding a DV camcorder

image stream, MPEG-2 or MPEG-4 decode. The processor is also capable of doing

all audio and video compression, decompression and processing necessary for bi-

directional video conferencing.

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