
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 15: Audio Output
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
15-17
21:8
Unused
-
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read
7
UDR_INTEN
R/W
0
UNDERRUN Interrupt Enable.
0 = No interrupt for UNDERRUN condition
1 = Interrupt if an UNDERRUN error occurs.
6
HBE_INTEN
R/W
0
HBE Interrupt Enable:
0 = No interrupt for HBE condition
1 = Interrupt if a data bus bandwidth error occurs.
5
BUF2_INTEN
R/W
0
Buffer 2 Empty Interrupt Enable:
0 = No interrupt when DMA buffer is empty.
1 = Interrupt if DMA buffer 2 in memory is empty.
4
BUF1_INTEN
R/W
0
Buffer 1 Empty Interrupt Enable:
0 = No interrupt when DMA buffer 1 is empty.
1 = Interrupt if DMA buffer 1 in memory is empty.
3
ACK_UDR
R/W
0
Write a 1 to clear the UNDERRUN ag and remove any pending
UNDERRUN interrupt request. ACK_UDR always reads 0.
2
ACK_HBE
R/W
0
Write a 1 to clear the HBE ag and remove any pending HBE
interrupt request. ACK_HBE always reads as 0.
1
ACK2
R/W
0
Write a 1 to clear the BUF2_EMPTYag and remove any pending
BUF2_EMPTY interrupt request. AO_BASE2 is then used to fetch
buffer1 data from memory. ACK2 always reads 0.
0
ACK1
R/W
0
Write a 1 to clear the BUF1_EMPTY ag and remove any pending
BUF1_EMPTY interrupt request. AO_BASE1 is then used to fetch
buffer1 data from memory. ACK1 always reads 0.
Offset 0x11 0008
AO_SERIAL—DTL Clock Domain
31
SER_MASTER
R/W
0
0 = The D/A subsystem is the timing master over the Audio Out
serial interface. SCK and WS act as inputs.
1 = AO is the timing master over serial interface. SCK and WS act
as outputs. This mode is required for 4, 6 or 8 channel operation.
The SER_MASTER bit should only be changed while Audio Out is
disabled i.e.,TRANS_ENABLE = 0.
30
DATAMODE
R/W
0
0 = Data is transmitted MSB rst.
1 = Data is transmitted LSB rst.
29
CLOCK_EDGE
R/W
0
0 = The parallel-to-serial converter samples WS on positive edges
of SCK and outputs data on the negative edge of SCK.
1 = The parallel-to-serial converter samples WS on negative edges
of SCK and outputs data on positive edges of SCK.
28:19
Unused
-
To ensure software backward compatibility unused or reserved bits must
be written as zeros and ignored upon read
.
18:17
NR_CHAN
R/W
00
00 = Only SD[0] is active.
01 = SD[0] and SD[1] are active.
10 = SD[0], SD[1], and SD[2] are active.
11 = SD[0], SD[1], SD[2] and SD[3] are active.
Each SD output receives either 1 or 2 channels depending on
TRANS_MODE. Non-active channels receive 0 value samples. In
mono modes, each channel of a SD output receives identical left
and right samples.
Table 9: Audio Output Port Registers …Continued
Bit
Symbol
Acces
s
Value
Description