
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
7-46
This aperture is for the SDRAM on the PNX15xx Series.
31:28
Base10 Address
R/W
0
Upper 4 bits of base10 address of the rst memory aperture
27:21
Base10 Address
R/W*
0
*The base 10 can be congured to various aperture sizes from 2
MB to 256 MB. (See pci_setup register). Depending on aperture
size selected, various bits will be R/W or Read Only.
Bit:
27
26
25
24
23
22
21
256M:
RO
128M:
RW
RO
64M:
RW
RO
32M:
RW
RO
16M:
RW
RO
8M:
RW
RO
4M:
RW
RO
2M:
RW
RO = Read-only bits read back as zero.
20:4
Reserved
R
0
3
Prefetchable
R
*cfg
Value is determined at boot time by the pci_setup register.
2:0
Type
R
0
Indicates type 0 memory space (locatable anywhere in 32-bit
address space).
Offset 0x0014
Base14 Address Register
This aperture will be set to 2 MB for MMIO on the PNX15xx Series.
31:28
Base14 Address
R/W
0001
Upper 4 bits of base14 address of the rst memory or IO aperture
27:21
Base14 Address
R/W*
1011111
*The base 14 can be congured to various aperture sizes from 2
MB to 256 MB. (See pci_setup register). Depending on aperture
size selected, various bits will be R/W or Read Only.
Bit:
27
26
25
24
23
22
21
256M:
RO
128M:
RW
RO
64M:
RW
RO
32M:
RW
RO
16M:
RW
RO
8M:
RW
RO
4M:
RW
RO
2M:
RW
RO = Read-only bits read back as zero.
20:4
Reserved
R
0
3
Prefetchable
R
*cfg
Value is determined at boot time by the pci_setup register.
2:0
Type
R
0
Indicates type 0 memory space (locatable anywhere in 32-bit
address space).
Offset 0x0018
Base18 Address Register
This aperture is for the XIO on the PNX15xx Series, which supports up to 128 MB of XIO memory space.
31:28
Base18 Address
R/W
0001
Upper 18 bits of base address of the rst memory or IO aperture
Table 9: PCI Conguration Registers
Bit
Symbol
Acces
s
Value
Description