
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 11: QVCP
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
11-50
27:16
INT_START_E
R/W
0
Horizontal offset for VSYNC start even eld (interlaced mode only)
Vsync appears at INT_START_E + 1.
15:12
Unused
-
11:0
INT_START_O
R/W
0
Horizontal offset for VSYNC start odd eld (interlaced mode only)
Vsync appears at INT_START_O + 1.
Offset 0x10 E030
VBI SRC Address
31:28
Unused
-
27:0
VBI_SRC_ADDR
R/W
0
VBI data source address
Offset 0x10 E034
VBI_CTRL
31:1
Unused
-
0
VBI_EN
R/W
0
Enable VBI data fetch engine.
Offset 0x10 E038
VBI_SENT_OFFSET
31:12
Unused
-
11:0
VBI_SENT_OFFSET
R/W
0
This programming value species the number of lines to add to the
linecnt value in the packet identier.
Offset 0x10 E03C
OUT_CTRL
31:25
Unused
-
24
TC_outS1R/Y
R/W
1
Set to unsigned format for the Y/R channel of the D1 slice:
1 = invert the MSB of the Y/R channel for the D1 slice
0 = leave D1 slice untouched
23
TC_outS1G/U
R/W
1
Set to unsigned format for the U/G channel of the D1 slice:
1 = invert the MSB of the U/G channel for D1 slice
0 = leave D1 slice untouched
22
TC_outS1B/V
R/W
1
Set to unsigned format for the V/B channel of the D1 slice:
1 = invert the MSB of the V/B channel for D1 slice
0 = leave D1 slice untouched
21
DNS1
R/W
0
444:422 down sample enable
1 = down sample lter enabled
0 = down sample lter bypassed
20:19
Unused
-
18
Qualier
R/W
0
1 = slice qualier is put out
0 = hsync is put out
17:16
Outmode
R/W
0
00 = output interface runs is d1 mode
01 = output interface runs in double-d1 mode
10 = output interface operates in up to 30 bit parallel mode
11 = unused
15
parallel_mode
R/W
0
This bit controls the sync delay compensation.
1 = syncs are delayed (needed for 24-bit parallel output mode)
0 = no additional sync delay
14:13
Unused
-
Table 20: QVCP 1 Registers …Continued
Bit
Symbol
Acces
s
Value
Description