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參數(shù)資料
| 型號： | 935270523557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64 |
| 文件頁數(shù)： | 89/93頁 |
| 文件大?。?/td> | 2118K |
| 代理商： | 935270523557 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
9 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
8.2 DMA mode
The ISP1160 also provides the DMA mode for external microprocessors to access its
internal FIFO buffer RAM. Data can be transferred by the DMA operation between a
microprocessor’s system memory and the ISP1160’s internal FIFO buffer RAM. Note:
the DMA operation must be controlled by the external microprocessor system’s DMA
controller (Master). Figure 4 shows the DMA interface between a microprocessor
system and the ISP1160. The ISP1160 provides a DMA channel controlled by DREQ
for DACK signals for the DMA transfer between a microprocessor’s system memory
and the ISP1160 HC’s internal FIFO buffer RAM. The EOT signal is an external
end-of-transfer signal used to terminate the DMA transfer. Some microprocessors
may not have this signal. In this case, the ISP1160 provides an internal EOT signal to
terminate the DMA transfer as well. Setting the HcDMAConguration register
(21H - Read, A1H - Write) enables the ISP1160’s HC internal DMA counter for the
DMA transfer. When the DMA counter reaches the value set in the
HcTransferCounter (22H - Read, A2H - Write) register to be used as the byte count of
the DMA transfer, the internal EOT signal will be generated to terminate the DMA
transfer.
Fig 3.
Programmed I/O interface between a microprocessor and the ISP1160.
004aaa061
D[15:0]
RD
WR
CS
A1
MICRO-
PROCESSOR
ISP1160
D[15:0]
P bus I/F
RD
WR
CS
A0
IRQ1
INT
Fig 4.
DMA interface between a microprocessor and the ISP1160.
004aaa062
D[15:0]
RD
WR
DACK1
DREQ1
EOT
MICRO-
PROCESSOR
ISP1160
D[15:0]
P bus I/F
RD
WR
DACK
DREQ
EOT
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