參數(shù)資料
型號: 935270523557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 5/93頁
文件大小: 2118K
代理商: 935270523557
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
13 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
In both gures, the DMA transfer is congured such that DREQ is active HIGH and
DACK is active LOW.
8.6 Interrupts
The ISP1160 has an interrupt request pin INT.
8.6.1
Pin conguration
The interrupt output signals have four conguration modes:
Level trigger, active LOW
Level trigger, active HIGH
Edge trigger, active LOW
Edge trigger, active HIGH.
Figure 12 shows these four interrupt conguration modes. They are programmable
through register settings, which are also used to disable or enable the signals.
N = 1/2 byte count of transfer data.
Fig 10. DMA transfer in single-cycle mode.
004aaa103
DREQ
DACK
D[15:0]
EOT
data #1
data #2
data #N
RD or WR
N = 1/2 byte count of transfer data, K = number of cycles/burst.
Fig 11. DMA transfer in burst mode.
004aaa104
data #1
data #K
data #2K
data #N
data #(K
+1)
data #(N
K+1)
DREQ
DACK
D[15:0]
EOT
RD or WR
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