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參數(shù)資料
| 型號： | 935270523557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64 |
| 文件頁數(shù)： | 57/93頁 |
| 文件大小： | 2118K |
| 代理商： | 935270523557 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
60 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Code (Hex): 21 — read
Code (Hex): A1 — write
10.4.3
HcTransferCounter register (22H—Read, A2H—Write)
This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer,
the number of bytes being read or written to the Isochronous Transfer List (ITL) or
Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a
DMA transfer, the number of bytes must be written into this register as well. However,
for this counter to be read into the DMA counter, the HCD must set bit 2 of the
HcDMAConguration register. The counter value for ATL must not be greater than
1000H, and for ITL it must not be greater than 800H. When the byte count of the data
transfer reaches this value, the HC will generate an internal EOT signal to set bit 2
AllEOInterrupt, of the Hc
PInterrupt register, and also update the HcBufferStatus
register.
Code (Hex): 22 — read
Code (Hex): A2 — write
4
DMAEnable
0 — DMA is terminated
1 — DMA is enabled
This bit will be reset to logic 0 when DMA transfer is completed.
3
-
reserved
2
DMACounter
Select
0 — DMA counter not used. External EOT must be used
1 — enables the DMA counter for DMA transfer.
HcTransferCounter register must be lled with non-zero values for
DREQ to be raised after bit DMA Enable is set.
1
ITL_ATL_
DataSelect
0 — ITL buffer RAM selected for ITL data
1 — ATL buffer RAM selected for ATL data
0
DMARead
WriteSelect
0 — read from the ISP1160 HC’s FIFO buffer RAM
1 — write to the ISP1160 HC’s FIFO buffer RAM
Table 39:
HcDMAConguration register: bit description…continued
Bit
Symbol
Description
Table 40:
HcTransferCounter register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
Counter value
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
Counter value
Reset
00000000
Access
R/W
Table 41:
HcTransferCounter register: bit description
Bit
Symbol
Description
15 to 0
Counter
value
The number of data bytes to be read to or written from RAM.
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