參數(shù)資料
型號: 935270523557
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù): 50/93頁
文件大?。?/td> 2118K
代理商: 935270523557
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
54 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
is in progress when a write to change port status occurs, the resulting port status
change must be postponed until the transaction completes. Reserved bits should
always be written logic 0.
Table 34:
HcRhPortStatus[1:2] register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
PRSC
OCIC
PSSC
PESC
CSC
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
LSDA
PPS
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
PRS
POCI
PSS
PES
CCS
Reset
00000000
Access
R/W
Table 35:
HcRshPortStatus[1:2] register: bit description
Bit
Symbol
Description
31 to 21
-
reserved
20
PRSC
PortResetStatusChange: This bit is set at the end of the 10 ms
port reset signal. The HCD writes a logic 1 to clear this bit. Writing
a logic 0 has no effect.
0 — port reset is not complete
1 — port reset is complete
19
OCIC
PortOverCurrentIndicatorChange: This bit is valid only if
overcurrent conditions are reported on a per-port basis. This bit is
set when Root Hub changes the PortOverCurrentIndicator bit. The
HCD writes a logic 1 to clear this bit. Writing a logic 0 has no
effect.
0 — no change in PortOverCurrentIndicator
1 — PortOverCurrentIndicator has changed
18
PSSC
PortSuspendStatusChange: This bit is set when the full resume
sequence has been completed. This sequence includes the 20 s
resume pulse, LS EOP, and 3 ms re-synchronization delay. The
HCD writes a logic 1 to clear this bit. Writing a logic 0 has no
effect. This bit is also cleared when ResetStatusChange is set.
0 — resume is not completed
1 — resume is completed
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