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參數(shù)資料
| 型號： | 440SP |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440SP Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 440SP |
| 文件頁數(shù)： | 79/85頁 |
| 文件大?。?/td> | 615K |
| 代理商： | 440SP |
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PowerPC 440SP Embedded Processor
80
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
DDR SDRAM Read Operation
The read of the incoming data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The data must be centered on these edges for correct operation.
The PPC440SP can delay in very small increments the DQS by means of the programming of the
MCIF0_RODC[RQFD] register field.
DDR SDRAM MemClkOut0 and Read Clock Delay
To accommodate timing variations introduced by the system designs using this chip, the three-stage data path
shown in Figure 9, below, is used to eliminate metastability and allow data sampling to be adjusted for minimum
latency. The data is stored in the eight Flip Flops of Stage 1, so that it can be transferred later, within an 8X period.
Figure 9. DDR SDRAM Read Data Path.
PLB bus
DQ
MCIF0_RQDC[RQFD]
Programmed
Delay
Package
Mux
Read DQS
C
D
FF: Flip-Flop
Q2
DQS
(Diff)
DDR 1X Clock
Mux
Data
(x64)
Read FIFO
PLB 1X Clock
Stage 2
Stage 1
Stage 3
FF
PLB bus
[0:63]
[64:127]
DQS Rising
DQS Falling
Q3
0
6
4
2
(x64)
Coarse Delay
Cycles
Driver
Rec
MemDCFdbkD
MemDCFdbkR
Ext FeedBack
Read Start
Feedback
Data Capture
Window
DDR 1X Clock
MCIF0_RDCC[RDSS]
MCIF0_RFDC[RFFD]
MCIF0_RFDC[RFOS]
Stage 2 Store
Oversampling
DQS aligned
CAS Lat Delay
FeedBack
Signal Gen
Fine Delay
T1 T2 T3 T4
Fine Delay
FF
7
5
3
1
0
7
Edge Sync
Upper
Lower
Signals
pins
FF
Q2_Ovs
FF
FBK signal
Delay
+1
Compare
DDR 1X Clock
Oversampling
Clock
Read Latency adjust circuit
C
D
FF
adjust
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|---|---|
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