參數(shù)資料
型號: 440SP
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 440SP Embedded Processor
中文描述: 嵌入式處理器的PowerPC 440SP
文件頁數(shù): 72/85頁
文件大?。?/td> 615K
代理商: 440SP
PowerPC 440SP Embedded Processor
74
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
System Interface
Halt
n/a
async
GPIO00:31
19.1
8.7
async
SysClk
n/a
SysErr
n/a
19.1
8.7
async
SysPartSel
n/a
async
SysReset
n/a
async
HISRRst
19.1
8.7
async
TestEn
n/a
async
TmrClk
n/a
Trace Interface
TrcClk
n/a
19.1
8.7
TrcBS0:2
19.1
8.7
TrcES0:4
19.1
8.7
TrcTS0:6
19.1
8.7
Table 14. I/O Specifications—All Speeds
(Sheet 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133.33MHz. PCI-X input setup time requirement is 1.2ns for 133.33MHz
and 1.7ns for 66.66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66.66MHz. PCI output hold time
requirement is 1ns for 66.66MHz and 2ns for 33.33MHz.
3. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
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