參數(shù)資料
型號： 440SP
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 440SP Embedded Processor
中文描述： 嵌入式處理器的PowerPC 440SP
文件頁數(shù)： 45/85頁
文件大?。?/td> 615K
代理商： 440SP
PowerPC 440SP Embedded Processor
Revision 1.23 - Sept 26, 2006
AMCC Proprietary
5
Data Sheet
PPC440SP Functional Block Diagram
Figure 2. PPC440SP Functional Block Diagram
The PPC440SP is a System on a chip, which uses IBM CoreConnect Bus Architecture.
Implemented with the Crossbar option, the IBM CoreConnect buses provide:
128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data
paths (10.6GB/sec total)
32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various processor accessible address regions. The second address
map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the
PPC440SP processor through the use of mtdcr and mfdcr instructions.
UART2
UART1
IIC1
Processor Core
DCR Bus
32KB
On-chip Peripheral Bus (OPB)
GPIO
Accelerator
Bridge
DDR2 SDRAM
External
Bus Controller
Controller
Clock,
Control,
Reset
Power
Mgmt
JTAG
Timers
MMU
Unit
OPB
Interrupt
Controller
Universal
I-Cache
32KB
D-Cache
XOR/DMA
PPC440
DDR PCI-X
MAL
Ethernet
DCRs
GPT
L2 Cache/SRAM
10/100/
Low Latency (LL) Segment
High Bandwidth (HB) Segment
Controller
Processor Local Bus (PLB)
Trace
Arbiter
PLB
I2O/DMA
Host
Local
64 bits
Local
32 bits
Memory
PCI0
PCI1
PCI2
1000
MII,
GMII
(EBC)
(DMA0 and
DMA1)
(DMA2)
Queue
IIC0
UART0
(EMAC)
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相關代理商/技術參數(shù)
參數(shù)描述
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440SS001M09 制造商:GLENAIR 制造商全稱:Glenair, Inc. 功能描述:EMI/RFI Crimp Ring Adapter Direct Coupling - Standard Profile
440SS001M10 制造商:GLENAIR 制造商全稱:Glenair, Inc. 功能描述:EMI/RFI Crimp Ring Adapter Direct Coupling - Standard Profile
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