參數(shù)資料
型號(hào): 440SP
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 440SP Embedded Processor
中文描述: 嵌入式處理器的PowerPC 440SP
文件頁數(shù): 76/85頁
文件大小: 615K
代理商: 440SP
PowerPC 440SP Embedded Processor
78
AMCC Proprietary
Revision 1.23 - Sept 26, 2006
Data Sheet
DDR SDRAM Write Operation
The following timing chart shows the relationship between the signals involved in a DDR write operation.
Figure 8. DDR SDRAM Write Cycle Timing
DDR SDRAM Read and Write I/O Timing—TSA and THA
Note 1: Clock speed is 333 MHz. TSA and THA are referenced to MemClkOut.
Note 2: Memory clock signal is shifted by 90
° from the internal clock.
Table 17. DDR SDRAM Read and Write I/O Timing—TSA and THA
Signal Name
TSA (ns)
THA (ns)
Minimum
MemAddr00:12
1.32
1.2
BA0:1
1.15
1.49
BankSel0:3
1.12
1.52
ClkEn0:3
1.29
1.45
CAS
1.24
1.14
RAS
1.29
1.48
WE
1.35
1.43
DQS
MemData
PLB Clk
MemClkOut
Addr/Cmd
TSA
THA
TDS
TSD
THD
TSD
THD
TSA = Setup time for address and command signals to MemClkOut
THA = Hold time for address and command signals from MemClkOut
TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS
TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
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