參數(shù)資料
型號(hào)： 440GX
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GX Embedded Processor
中文描述： 超出了Power PC嵌入式處理器
文件頁數(shù)： 85/93頁
文件大?。?/td> 794K
代理商： 440GX
440GX – Power PC 440GX Embedded Processor
86
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
Example 1:
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage
1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically
close to the PPC440GX, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary
to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example
TT = 1.27ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 1
DQS at pin
PLB Clock
TSIN
TDIN = Delay from data at package pin to D on Stage 1 FF.
TSIN = Delay from DQS at package pin to C on Stage 1 FF.
Data at pin
D0
D1
D2
D3
DQS Stage 1 C
D0
D1
D2
D3
TDIN
D0
D2
Data in Stage 1 D
D1
D3
Data out Stage 1
High
Low
TP
D0
D2
D1
D3
Data in at RDSP
High
Low
with no ECC
TT
TP = Propagation delay through FFs
TT = Propagation delay, Stage 1 input to RDSP input w/o ECC
D0
D2
D1
D3
Data out RDSP
High
Low
(1)
D2
TP
D0
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