參數(shù)資料
型號: 440GX
廠商: Applied Micro Circuits Corp.
英文描述: Power PC 440GX Embedded Processor
中文描述: 超出了Power PC嵌入式處理器
文件頁數(shù): 69/93頁
文件大小: 794K
代理商: 440GX
440GX – Power PC 440GX Embedded Processor
AMCC
71
Revision 1.15 – August 30, 2007
Data Sheet
Ethernet MII Interface
EMCRxD0:3
4
1
na
5.1
6.8
EMCRxClk
1
EMCRxDV
4
1
na
5.1
6.8
EMCRxClk
1
EMCRxClk
na
5.1
6.8
1,
async
EMCRxErr
4
1
na
5.1
6.8
EMCRxClk
1
EMCTxD0:3
na
15
2
5.1
6.8
EMCTxClk
1
EMCTxEn
na
15
2
5.1
6.8
EMCTxClk
1
EMCTxClk
na
1,
async
EMCTxErr
na
15
2
5.1
6.8
EMCTxClk
1
EMCCrS
na
5.1
6.8
1,
async
EMCCD
na
5.1
6.8
1,
async
EMCMDIO
5.1
6.8
EMCMDClk
1
EMCMDClk
na
5.1
6.8
1,
async
Ethernet RMII Interface
EMC0RxD0:1
2
1
na
5.1
6.8
EMCRefClk
EMC0RxErr
2
1
na
5.1
6.8
EMCRefClk
EMC0CrSDV
na
5.1
6.8
EMCRefClk
EMC0TxD0:1
na
11
2
5.1
6.8
EMCRefClk
EMC0:1TxEn
na
11
2
5.1
6.8
EMCRefClk
EMC1RxD0:1
na
5.1
6.8
EMCRefClk
EMC1RxErr
na
5.1
6.8
EMCRefClk
EMC1CrSDV
na
5.1
6.8
EMCRefClk
EMC1TxD0:1
na
11
2
5.1
6.8
EMCRefClk
na
3,
async
I/O Specifications—All Speeds (Sheet 2 of 7)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Signal
Input (ns)
Output (ns)
Output Current (mA)
Clock
Notes
Setup Time
(TIS min)
Hold Time
(TIH min)
Valid Delay
(TOV max)
Hold Time
(TOH min)
I/O H
(minimum)
I/O L
(minimum)
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