參數(shù)資料
型號： 440GX
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GX Embedded Processor
中文描述： 超出了Power PC嵌入式處理器
文件頁數(shù)： 2/93頁
文件大?。?/td> 794K
代理商： 440GX
440GX – Power PC 440GX Embedded Processor
10
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
PowerPC 440 Processor Core
The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, ISCSI, routers,
switches, printers, set-top boxes, etc. It is the first processor core to implement the Book E PowerPC embedded
architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
Up to 800MHz operation
PowerPC Book E architecture
32KB I-cache, 32KB D-cache
- UTLB Word Wide parity on data and tag address parity with exception force
Three logical regions in D-cache: locked, transient, normal
D-cache full line flush capability
41-bit virtual address, 36-bit (64GB) physical address
Superscalar, out-of-order execution
7-stage pipeline
3 execution pipelines
Dynamic branch prediction
Memory management unit
- 64-entry, full associative, unified TLB with parity
- Separate instruction and data micro-TLBs
- Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
Debug facilities
- Multiple instruction and data range breakpoints
- Data value compare
- Single step, branch, and trap events
- Non-invasive real-time trace interface
24 DSP instructions
- Single-cycle multiply and multiply-accumulate
- 32 x 32 integer multiply
- 16 x 16 -> 32-bit MAC
Internal Buses
The PowerPC 440GX features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip
Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores
such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI-X bridge connect to
the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for
passing status and control information between the processor core and the other on-chip cores.
Features include:
PLB
- 128-bit implementation of the PLB architecture
- Separate and simultaneous read and write data paths
- 64-bit address
- Simultaneous control, address, and data phases
- Four levels of pipelining
- Byte enable capability supporting unaligned transfers
- 32- and 64-byte burst transfers
- 166MHz, maximum 5.2GB/s (simultaneous read and write)(200MHz for 800MHz Rev F parts)
- Processor:bus clock ratios of N:1 and N:2
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
440HA002M1507-N 功能描述:環(huán)形MIL規(guī)格后蓋 RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy
440HA002N2312-C 功能描述:環(huán)形MIL規(guī)格后蓋 RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy
440HA002NF0902-N 功能描述:環(huán)形MIL規(guī)格后蓋 RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy
440HA002NF0903-N 功能描述:環(huán)形MIL規(guī)格后蓋 RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy
440HA002NF1102-N 功能描述:環(huán)形MIL規(guī)格后蓋 RoHS:否 制造商:Amphenol PCD MIL 類型:MIL-DTL-38999 III, IV 系列:AS85049 產(chǎn)品類型:Environmental EMI/RFI Backshells 外殼類型:Straight 外殼大小:18 外殼材質(zhì):Aluminum Alloy
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