參數(shù)資料
型號(hào)： 440GX
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GX Embedded Processor
中文描述： 超出了Power PC嵌入式處理器
文件頁(yè)數(shù)： 50/93頁(yè)
文件大?。?/td> 794K
代理商： 440GX
440GX – Power PC 440GX Embedded Processor
54
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
PerOE
Used by either peripheral controller or DMA controller depending
upon the type of transfer involved. When the PPC440GX is the
bus master, it enables the selected device to drive the bus.
O
3.3V LVTTL
2
PerPar0:3
External peripheral data bus byte parity.
I/O
3.3V LVTTL
1
PerReady
Used by a peripheral slave to indicate it is ready to transfer data.
I
3.3V LVTTL
PerR/W
Used by the PPC440GX when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to indicate
the direction of transfer.
I/O
3.3V LVTTL
1, 2
PerWE
Write Enable. Low when any of the four PerWBE0:3 signals are
low.
O
3.3V LVTTL
2
External Master Peripheral Interface
BusReq
Bus Request. Used when the PPC440GX needs to regain control
of peripheral interface from an external master.
O
3.3V LVTTL
ExtAck
External Acknowledgement. Used by the PPC440GX to indicate
that a data transfer occurred.
O
3.3V LVTTL
ExtReq
External Request. Used by an external master to indicate it is
prepared to transfer data.
I
3.3V LVTTL
1, 4
ExtReset
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
O
3.3V LVTTL
HoldAck
Hold Acknowledge. Used by the PPC440GX to transfer ownership
of peripheral bus to an external master.
O
3.3V LVTTL
HoldReq
Hold Request. Used by an external master to request ownership
of the peripheral bus.
I
3.3V LVTTL
1, 5
PerClk
Peripheral Clock. Used by an external master and by synchronous
peripheral slaves.
O
3.3V LVTTL
PerErr
External Error. Used as an input to record external master errors
and external slave peripheral errors.
I/O
3.3V LVTTL
1, 5
UART Peripheral Interface
UARTSerClk
Serial clock input that provides an alternative to the internally
generated serial clock. Used in cases where the allowable
internally generated clock rates are not satisfactory. This input can
be individually connected to either or both UART0 and UART1.
I
3.3V LVTTL
1, 4
UART0_Rx
UART0 Receive data.
I
3.3V LVTTL
1, 4
UART0_Tx
UART0 Transmit data.
O
3.3V LVTTL
4
UART0_DCD
UART0 Data Carrier Detect.
I
3.3V LVTTL
6
UART0_DSR
UART0 Data Set Ready.
I
3.3V LVTTL
6
UART0_CTS
UART0 Clear To Send.
I
3.3V LVTTL
1, 4
UART0_DTR
UART0 Data Terminal Ready.
O
3.3V LVTTL
4
UART0_RTS
UART0 Request To Send.
O
3.3V LVTTL
4
UART0_RI
UART0 Ring Indicator.
I
3.3V LVTTL
1, 4
Signal Functional Description (Sheet 5 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to 3.3V)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
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