參數(shù)資料
型號: 440GX
廠商: Applied Micro Circuits Corp.
英文描述: Power PC 440GX Embedded Processor
中文描述: 超出了Power PC嵌入式處理器
文件頁數(shù): 6/93頁
文件大?。?/td> 794K
代理商: 440GX
440GX – Power PC 440GX Embedded Processor
14
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
Support for peripherals running on slower frequency buses
Serial Port
Features include:
One 8-pin UART and one 4-pin UART interface provided
Selectable internal or external serial clock to allow wide range of baud rates
Register compatibility with 16750 register set
Complete status reporting capability
Fully programmable serial-interface characteristics
Supports DMA using internal DMA engine
IIC Bus Interface
Features include:
Two IIC interfaces provided
Support for Philips Semiconductors I2C Specification, dated 1995
Operation at 100kHz or 400kHz
8-bit data
10- or 7-bit address
Slave transmitter and receiver
Master transmitter and receiver
Multiple bus masters
Supports fixed VDD IIC interface
Two independent 4 x 1 byte data buffers
Twelve memory-mapped, fully programmable configuration registers
One programmable interrupt request signal
Provides full management of all IIC bus protocols
Programmable error recovery
General Purpose Timers (GPT)
Provides a separate time base counter and additional system timers in addition to those defined in the processor
core.
32-bit Time Base Counter driven by the OPB bus clock
Seven 32-bit compare timers
General Purpose IO (GPIO) Controller
Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master
accesses.
The 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO
capabilities acts as a GPIO or is used for another purpose.
Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,
tri-stated if output bit is 1).
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