參數(shù)資料
型號(hào)： 440GX
廠商： Applied Micro Circuits Corp.
英文描述： Power PC 440GX Embedded Processor
中文描述： 超出了Power PC嵌入式處理器
文件頁數(shù)： 46/93頁
文件大小： 794K
代理商： 440GX
440GX – Power PC 440GX Embedded Processor
50
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
Signal Functional Description (Sheet 1 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
Ω to 3.3V)
3. Must pull down (recommended value is 1k
Ω)
4. If not used, must pull up (recommended value is 3k
Ω to 3.3V)
5. If not used, must pull down (recommended value is 1k
Ω)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
PCI-X Interface
PCIXAD00:63
Address/Data bus (bidirectional).
I/O
3.3V PCI
PCIXC0:7[BE0:7]
PCI-X Command[Byte Enables]
.
I/O
3.3V PCI
PCIXCap
Capable of PCI-X operation.
I
3.3V LVTTL
5
PCIX133Cap
PCI-X devices are 133 MHz capable.
O
3.3V PCI
PCIXClk
Provides timing to the PCI interface for PCI transactions.
Note:If the PCI-X interface is not being used, drive this pin with a
3.3V clock signal at a frequency between 1 and 66MHz
I
3.3V PCI
PCIXDevSel
Indicates the driving device has decoded its address as the target
of the current access.
I/O
3.3V PCI
4
PCIXFrame
Driven by the current master to indicate beginning and duration of
an access.
I/O
3.3V PCI
4
PCIXGnt0
Indicates that the specified agent is granted access to the bus.
When using an external PCI/PCI-X arbiter, connect the external
arbiter's Grant line to this signal.
I/O
3.3V PCI
4
PCIXGnt1
Indicates that the specified agent is granted access to the bus.
I/O
3.3V PCI
4
PCIXGnt2:5
Indicates that the specified agent is granted access to the bus.
O
3.3V PCI
PCIXIDSel
Used as a chip select during configuration read and write
transactions.
I
3.3V PCI
5
PCIXINT
Level sensitive PCI interrupt.
O
3.3V PCI
PCIXIRDY
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
I/O
3.3V PCI
4
PCIXM66En
Capable of 66MHz operation.
I
3.3V LVTTL
w/pull-up
5
PCIXParHigh
Even parity across PCIAD32:63 and PCIXC0:3[BE4:7].
I/O
3.3V PCI
PCIXParLow
Even parity across PCIAD0:31 and PCIXC0:3[BE0:3].
I/O
3.3V PCI
PCIXPErr
Reports data parity errors during all PCI transactions except a
Special Cycle.
I/O
3.3V PCI
4
PCIXReq0
An indication to the PCI-X arbiter that the specified agent wishes
to use the bus. When using an external PCI/PCI-X arbiter, connect
the external arbiter's Request line to this signal.
I/O
3.3V PCI
4
PCIXReq1:5
An indication to the PCI-X arbiter that the specified agent wishes
to use the bus.
I
3.3V PCI
4
PCIXReq64
Asserted by the current bus master, indicating a 64-bit transfer.
I/O
3.3V PCI
4
PCIXAck64
Indicates the target can transfer data using 64 bits.
I/O
3.3V PCI
4
PCIXReset
Brings PCI device registers and logic to a consistent state.
O
3.3V PCI
PCIXSErr
Reports address parity errors, data parity errors on the Special
Cycle command, or other catastrophic system errors.
I/O
3.3V PCI
4
PCIXStop
Indicates the current target is requesting the master to stop the
current transaction.
I/O
3.3V PCI
4
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