參數(shù)資料
型號: 440GX
廠商: Applied Micro Circuits Corp.
英文描述: Power PC 440GX Embedded Processor
中文描述: 超出了Power PC嵌入式處理器
文件頁數(shù): 56/93頁
文件大小: 794K
代理商: 440GX
440GX – Power PC 440GX Embedded Processor
6
AMCC
Revision 1.15 – August 30, 2007
Data Sheet
PPC440GX Functional Block Diagram
The PPC440GX is designed using the IBM Microelectronics Blue Logic methodology in which major functional
blocks are integrated together to create an application-specific product (ASIC). This approach provides a
consistent way to create complex ASICs using IBM CoreConnect Bus Architecture.
Note: IBM CoreConnect buses provide:
128-bit PLB interfaces up to 200MHz
32-bit OPB interfaces up to 83.33MHz, 333MB/s
Address Maps
The PPC440GX incorporates two address maps. The first is a fixed processor system memory address map. This
address map defines the possible contents of various address regions which the processor can access. The
second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running
on the PPC440GX processor through the use of mtdcr and mfdcr instructions.
Processor Core
DCR Bus
32KB
On-chip Peripheral Bus (OPB)
GPIO
IIC
UART
DMA
Bridge
Processor Local Bus (PLB)
DDR SDRAM
External
Bus
Controller
Clock
Control
Reset
Power
Mgmt
JTAG
Trace
Timers
MMU
Controller
OPB
Interrupt
Controller
Arb
32-bit addr
32-bit data
13-bit addr
32/64-bit data
External
Bus Master
Controller
Universal
I-Cache
32KB
D-Cache
(4-Channel)
SRAM
256KB
PPC440
63 internal
18 external
PCI-X
Bridge
x2
MAL
Ethernet
x2
DCRs
1 GMII
or
2 RGMII
or
1 TBI
or
2 RTBI
GP
Timers
1 MII
or
2 RMII
or
4 SMII
ZMII
RGMII
I2O
Messaging
83MHz max
L2 Controller
10/100
TAH
10/100/
1000 x2
133MHz max
166MHz max
Bridge
32/64-bit data
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