參數(shù)資料
型號(hào)： HSP50216
廠商： Intersil Corporation
英文描述： Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器)
中文描述： 四通道可編程數(shù)字下變頻器（四通道可編程數(shù)字下變頻器）
文件頁(yè)數(shù)： 17/52頁(yè)
文件大?。?/td> 431K
代理商： HSP50216
3-17
62:53
Coefficient Memory
Block Start
Memory base address of coefficients, 0-1023, 0-511 are valid on the HSP50216.
63
Reserved
Set to 0
66:64
Coefficient Memory
Block Size
66:64
0
1
2
3
4
5
6
7
(Modulo addressing can be used, but is usually not needed. If not needed this bit field can always be set
to 7).
Memory Block Size
8
16
32
64
128
256
512
1024
75:67
Number of FIR
Outputs
Number of FIR outputs (range is 1 to 512, load w/ desired value minus 1).
This is usually equal to the total decimation that follows the filter.
84:76
Read Address
Pointer Step
Read address pointer step (for next run). This is usually equal to the filter decimation times the number
of outputs from the instruction.
93:85
Initial Address Offset
Initial address offset (to ADDRB). This is the offset from the start address to other end of filter.
For symmetric filters, usually equal to -1 x (number of taps -1).
95:94
Reserved
Set to 0
104:96
Memory Reads Per
FIR Output
This is based on the number of taps (load with value below minus 1).
Type
Symmetric, even number of taps
Symmetric, odd number of taps
Decimating HBF
Asymmetric
Complex
Resampling
Interpolating HBF
Value
(taps/2) or floor((taps+1)/2)
(taps+1)/2 or floor((taps+1)/2)
(taps+5)/4
taps
taps
taps/phase (six taps per phase for the ROM’d coefficients provided)
(taps+5)/4-1
106:105
Clocks Per
Memory Read
Set to 0 for all but complex FIR, which is set to 1.
115:107
Data Memory
Step Size 1
(ADDRA) Step size for all but the last tap computation of the FIR.
Set to -2 for HBF, -1 otherwise.
117:116
Data Memory
Step Size 2
(ADDRA) Step size for last tap computation. Set to -1.
117:116
Step size
0
0
1
-1
2
-2
3
step size value
119:118
Data Memory
Address Offset Step
(ADDRB) Step size for opposite end of symmetric filter. Set to +2 for Decimating HBF, to +1 for others
(the B data is not used for asymmetric, resampling, and complex filters).
INSTRUCTION BIT FIELDS (Continued)
BIT
POSITIONS
FUNCTION
DESCRIPTION
HSP50216
相關(guān)PDF資料
PDF描述
HSP50307 Burst QPSK Modulator(混合信號(hào)QPSK調(diào)制器)
HSP50415VI CABLE ASSEMBLY; 75 OHM TNC MALE TO 75 OHM TNC MALE; 75 OHM, RG6A/U COAX
HSP50415EVAL1 HSP50415EVAL1 Evaluation Kit
HSP9501 Programmable Data Buffer(可編程數(shù)據(jù)緩沖器)
HSP9520 Multilevel Pipeline Registers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP50216_06 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter
HSP50216_07 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter
HSP50216KI 功能描述:上下轉(zhuǎn)換器 MULTI-CHANNEL PROGRAMMABLE DOW CONVERTER,BGA PKG,IND TEMP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50216KIZ 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50306 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Digital QPSK Demodulator
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*