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參數資料
| 型號： | μPD30100 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-bit RISC Microprosessor(64位 RISC 微處理器) |
| 中文描述： | 64位RISC Microprosessor（64位的RISC微處理器） |
| 文件頁數： | 8/52頁 |
| 文件大小： | 365K |
| 代理商： | ΜPD30100 |
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8
μ
PD30100
2. INTERNAL BLOCK
(1) Execution unit
Executes integer operation instructions. This unit is provided with the 64-bit register file and data path.
(2) Coprocessor 0 (CP0)
This coprocessor is provided with the following:
Exception processing unit
Memory management unit
The memory management unit converts virtual addresses into physical addresses and checks memory access
between different memory segments (kernel, supervisor, and user).
TLB (translation lookaside buffer) converts virtual addresses into physical addresses.
The V
R
4100 supports five types of page size, 1K byte, 4K bytes, 16K bytes, 64K bytes and 256K bytes, with VSIZE
(virtual address) = 40 and PSIZE = (physical address) = 32. TLB has 32 entries. Each entry is mapped to an
even/odd page of a page frame number.
The exception processing unit is provided with system control coprocessor registers. For the data format of each
register, refer to
3.5 System Control Coprocessor (CP0)
.
(3) Pipeline control
The pipeline is controlled and appropriate processing is executed in the following cases:
Occurrence of cache miss
Multi-cycle instruction
Occurrence of system exception, etc.
(4) Instruction address
The execution address of the next instruction to be fetched is calculated.
For this purpose, the following units are provided:
PC incrementer
Branch address adder
Conditional branch address selector
(5) Instruction cache
The instruction cache employs the following methods:
Direct map
Virtual index address
Physical tag cache
The capacity of the instruction cache is 2K bytes. Each cache line consists of 4-word data and its word parity,
22-bit tag and its parity bit, and a valid bit.
The instruction cache data interface is 32 bits wide.
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