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| 型號： | μPD30100 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-bit RISC Microprosessor(64位 RISC 微處理器) |
| 中文描述： | 64位RISC Microprosessor（64位的RISC微處理器） |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 365K |
| 代理商： | ΜPD30100 |
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26
μ
PD30100
Table 3-4. Types of Exceptions
Exception
Abbreviation
Description
Cold reset
–
Occurs if ColdReset and Reset signals are simultaneously asserted active.
Aborts instruction execution and executes a handler on the reset vector.
The internal status is undefined, except some bits of the status register.
Soft reset
–
Occurs if Reset signal is asserted active.
Aborts instruction execution and executes a handler on the reset vector. The
internal status before soft reset is retained.
NMI
–
Non-maskable interrupt request by the external agent.
TLB unmatch
TLBL/TLBS
Occurs if the operating mode is the 32-bit mode and the number of TLB entries
matching the referenced address runs short.
Expansion
addressing
TLB unmatch
TLBL/TLBS
Occurs if the operating mode is 64-bit mode and the number of TLB entries
matching the referenced address runs short.
TLB invalid
TLBL/TLBS
Occurs if the TLB entry matching the referenced virtual address is invalid. (V bit = 0)
TLB change
Mod
Occurs if a TLB entry that coincides with virtual address to be accessed is valid but
write is disabled (D bit = 0) when the store instruction is executed
Bus error
IBE/DBE
Occurs if an external agent indicates a data error on the SysCmd bus by an external
interrupt to the bus interface (bus timeout, bus parity error, or invalid physical memory
address or access type)
Address error
AdEL/AdES
Occurs if an attempt is made to execute the LH, SH/LW/SW, LD, or SD instruction
to the half word/word/double word not at the half word/word/double word
boundary, or to reference a virtual address that cannot be accessed.
Integer overflow
Ov
Occurs if 2’s complement overflow occurs as a result of addition or subtraction.
Trap
Tr
Occurs if the condition is true at trap instruction execution.
System call
Sys
Occurs when the SYSCALL instruction is executed.
Breakpoint
Bp
Occurs when the BREAK instruction is executed.
Reserved
instruction
RI
Occurs when an instruction whose op code (bits 31-26) is undefined, or the
SPECIAL instruction whose op code (bits 5-0) is undefined is executed.
Coprocessor
unusable
CpU
Occurs if the coprocessor instruction is executed when the corresponding
coprocessor use enable bit is not set.
Interrupt
Int
Occurs when one of the eight interrupt sources becomes active.
Cache error
–
Occurs when a parity error is detected on the internal cache or system interface.
Watch
WATCH
Occurs when an attempt is made to reference the physical address in the watch
Lo/Hi register with the load/store instruction.
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