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參數(shù)資料
| 型號(hào)： | μPD30100 |
| 廠商： | NEC Corp. |
| 英文描述： | 64-bit RISC Microprosessor(64位 RISC 微處理器) |
| 中文描述： | 64位RISC Microprosessor（64位的RISC微處理器） |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 365K |
| 代理商： | ΜPD30100 |
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31
μ
PD30100
5. INTERNAL/EXTERNAL FUNCTION
5.1 Reset Functions
The V
R
4100 has two reset signals: cold reset (ColdReset) and soft reset (Reset). Setting of the necessary
mode is controlled directly by pins and the config register.
5.1.1 Cold reset
This reset operation initializes all the information of the CPU.
The following registers are set to the values shown at cold reset.
TS and SR bits of status register ... 0
ERL and BEV bits of status register ... 1
Random register ... upper-limit value
Wired register ... 0
Cold reset is executed when the ColdReset and Reset signals are made active.
5.1.2 Software reset
This reset operation can be executed when the Reset signal is asserted active. This reset does not perform
initialization, and the status before reset is retained as much as possible. However, if a multi-cycle instruction
is aborted by this reset, the result is undefined.
5.2 Interrupt Functions
There are two major categories of interrupt requests as follows:
Maskable interrupt requests
Non-maskable interrupt (NMI) requests
(1) Maskable interrupt requests
These interrupts undergo mask control. The mask processing is performed by the status register. (Each interrupt
can be handled individually, or interrupts can be handled as a group.)
There is no priority among interrupts.
(a) Hardware interrupt request (5 causes)
Accepted by activating an external write request or Int (4:0) signal.
(b) Software interrupt request (2 causes)
Accepted by setting the cause register IP0 and IP1 bits.
(c) Timer interrupt request (1 cause)
If the value of the count register becomes equal to that of the compare register, the cause register IP7 bit
is set and the interrupt is accepted.
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