參數(shù)資料
型號(hào): μPD30100
廠商: NEC Corp.
英文描述: 64-bit RISC Microprosessor(64位 RISC 微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁數(shù): 16/52頁
文件大?。?/td> 365K
代理商: ΜPD30100
16
μ
PD30100
3.5 System Control Coprocessor (CP0)
The CP0 supports memory management, address conversion, exception processing, and privileged operation.
CP0 has the registers shown in Table 3-3 and a 32-entry TLB.
Although the basic configuration of the CP0 register of the V
R
4100 is the same as that of the V
R
4200 and
V
R
4400, the bit configuration and the settings differ because the number of entries of the TLB, page size, cache
size, physical address space, and system interface differ. For details, refer to
V
R
4100 User’s Manual
.
3.5.1 CP0 registers
All the CP0 registers of the V
R
4100 that can be used are listed below. Writing or reading an unused register
(RFU) is undefined. In the 32-bit mode, the higher 32 bits of the 64-bit registers are masked.
Figure 3-6. CP0 Registers and TLB
Remark
“*” denotes a register number.
Entry Hi
10*
Index
0 *
Entry Lo0
2 *
Entry Lo1
3 *
Random
1 *
Page mask
5 *
Wired
6 *
Config
16*
Tag Lo
28*
(
Safety
) entry
PRld
15*
Tag Hi
29*
LLAddr
17*
TLB
31
0
0
127/255
Compare
11*
Count
9 *
Status
12*
Cause
13*
Watch Lo
18*
Parity error
26*
Cache error
27*
Error EPC
30*
EPC
14*
X Context
20*
Watch Hi
19*
Context
4 *
BadVAddr
8 *
Registers used by memory management system
Registers used for exception processing
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