參數(shù)資料
型號: μPD30100
廠商: NEC Corp.
英文描述: 64-bit RISC Microprosessor(64位 RISC 微處理器)
中文描述: 64位RISC Microprosessor(64位的RISC微處理器)
文件頁數(shù): 6/52頁
文件大小: 365K
代理商: ΜPD30100
6
μ
PD30100
1. PIN FUNCTIONS
Pin Name
I/O
Function
SysAD (31:0)
I/O
System address/data bus.
32-bit bus for communication between processor and external agent.
SysADC (3:0)
I/O
System address/data check bus.
4-bit bus for checking SysAD bus.
SysCmd (4:0)
I/O
System command/data ID bus.
5-bit bus for communication of commands and data identifiers between processor and
external agent.
SysCmdP
I/O
System command/data ID bus parity.
1-bit bus even number parity bit for SysCmd.
EValid
Input
External valid.
Signal indicating that external agent has transmitted valid address or data onto SysAD bus
and valid command or data identifier onto SysCmd bus.
PValid
Output
Processor valid.
Signal indicating that processor has transmitted valid address or data onto SysAD bus and
valid command or data identifier onto SysCmd bus.
EReq
Input
External request.
Signal used by external agent to request for issuance by system interface.
PReq
Output
Processor request.
Signal used by processor to request for issuance by system interface.
PMaster
Output
Processor master.
Signal indicating that processor controls system interface.
ERdy
Input
External ready.
Signal indicating that external agent can accept processor request.
Fault
Output
Fault.
Signal indicating that a parity error has occurred in SysCmd bus.
Int (4:0)
Input
Interrupt.
General-purpose processor interrupt requests whose input statuses can be confirmed by
bits 14 through 10 of cause register.
NMI
Input
Non-maskable interrupt.
Interrupt request that cannot be masked.
ColdReset
Input
Cold reset.
Signal that initializes internal status of processor.
Reset
Input
Reset.
Signal that generates reset exception without initializing internal status of processor.
MasterClock
Input
Master clock.
Clock input signal to processor.
MasterOut
Output
Master clock output.
Output of master clock synchronized with master clock.
TClock
Output
Transmit clock.
Transmit clock of system interface.
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