參數(shù)資料
型號(hào)： μPD30100
廠商： NEC Corp.
英文描述： 64-bit RISC Microprosessor(64位 RISC 微處理器)
中文描述： 64位RISC Microprosessor（64位的RISC微處理器）
文件頁(yè)數(shù)： 34/52頁(yè)
文件大?。?/td> 365K
代理商： ΜPD30100
34
μ
PD30100
Table 6-1. CPU Instruction Set: ISA (1/3)
op
base
rt
offset
Instructions
Description
Format
Load/store instruction
LB
Load Byte
LB
rt, offset (base)
LBU
Load Byte Unsigned
LBU
rt, offset (base)
LH
Load Halfword
LH
rt, offset (base)
LHU
Load Halfword Unsigned
LHU
rt, offset (base)
LW
Load Word
LW
rt, offset (base)
LWL
Load Word Left
LWL
rt, offset (base)
LWR
Load Word Right
LWR
rt, offset (base)
SB
Store Byte
SB
rt, offset (base)
SH
Store Halfword
SH
rt, offset (base)
SW
Store Word
SW
rt, offset (base)
SWL
Store Word Left
SWL
rt, offset (base)
SWR
Store Word Right
SWR
rt, offset (base)
ALU immediate instruction
ADDI
Add Immediate
ADDI
rt, rs, immediate
ADDIU
Add Immediate Unsigned
ADDIU
rt, rs, immediate
SLTI
Set On Less Than Immediate
SLTI
rt, rs, immediate
SLTIU
Set On Less Than Immediate Unsigned
SLTIU
rt, rs, immediate
ANDI
And Immediate
ANDI
rt, rs, immediate
ORI
Or Immediate
ORI
rt, rs, immediate
XORI
Exclusive Or Immediate
XORI
rt, rs, immediate
LUI
Load Upper Immediate
LUI
rt, immediate
3-operand type instruction
ADD
Add
ADD
rd, rs, rt
ADDU
Add Unsigned
ADDU
rd, rs, rt
SUB
Subtract
SUB
rd, rs, rt
SUBU
Subtract Unsigned
SUBU
rd, rs, rt
SLT
Set On Less Than
SLT
rd, rs, rt
SLTU
Set On Less Than Unsigned
SLTU
rd, rs, rt
AND
And
AND
rd, rs, rt
OR
Or
OR
rd, rs, rt
XOR
Exclusive Or
XOR
rd, rs, rt
NOR
Nor
NOR
rd, rs, rt
Shift instruction
SLL
Shift Left Logical
SLL
rd, rt, sa
SRL
Shift Right Logical
SRL
rd, rt, sa
SRA
Shift Right Arithmetic
SRA
rd, rt, sa
SLLV
Shift Left Logical Variable
SLLV
rd, rt, rs
SRLV
Shift Right Logical Variable
SRLV
rd, rt, rs
SRAV
Shift Right Arithmetic Variable
SRAV
rd, rt, rs
op
rs
rt
rd
sa
funct
op
rs
rt
rd
sa
funct
op
rs
rt
offset
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