參數(shù)資料
型號(hào)： μPD30100
廠商： NEC Corp.
英文描述： 64-bit RISC Microprosessor(64位 RISC 微處理器)
中文描述： 64位RISC Microprosessor（64位的RISC微處理器）
文件頁(yè)數(shù)： 14/52頁(yè)
文件大小： 365K
代理商： ΜPD30100
14
μ
PD30100
3.4 Overview of Instruction Set
The instruction set of the V
R
4100 conforms basically to the MIPS-I, -II, and -III instruction sets. However,
it differs from the instructions set of the other processors in the V
R
series in the following four points:
(1) Deletion of floating-point (FPU) instructions
Because the V
R
4100 does not have a floating-point unit, it does not support FPU instructions. If an FPU instruction
is executed, therefore, a reserved instruction exception occurs. If it is necessary to use an FPU instruction,
emulate it by software in an exception handler.
(2) Deletion of multi-processor instructions
The V
R
4100 does not support the operating environment of a multi-processor system. If a synchronization support
instruction (LL or SC instruction) defined by MIPS-II and -III ISA is executed, therefore, reserved instruction
exception occurs. For the above reason, the V
R
4100 is not provided with a load link bit (LL bit).
The V
R
4100 executes all the load/store instructions in the sequence specified in the program. Therefore, the
SYNC instruction is treated as a NOP instruction.
(3) Addition of sum-of-products instructions
The V
R
4100 has a dedicated sum-of-products core in the CPU and integer sum-of-products instructions to
increase the speed of sum-of-products operations. These instructions are not correctly executed by the other
processors in the V
R
series.
The operations of the sum-of-products instructions are given below.
(a) MADD16 (Multiply and Add 16-bit Integer)
Multiplies the contents of general-purpose register rs by the contents of general-purpose register rt. Both
the operands are treated as 16-bit signed integers. The bits 62 through 15 of both the operands must be
sign-extended values.
The result of the multiplication is added to the 64-bit value of the special registers HI and LO.
The lower word of the 64-bit result is loaded to special register LO, and the higher word is loaded to special
register HI.
An integer overflow exception does not occur.
Figure 3-5 shows the MADD16 instruction operation outline.
Figure 3-5. MADD16 Instruction Operation
rs
rt
31
15
General-purpose register file
MUL
ADD
HI
LO
63
31
Higher
Lower
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