
37
μ
PD30100
Table 6-2. CPU Instruction Set: Expansion ISA (2/2)
REGIMM
rs
sub
immediate
op
rs
rt
rd
sa
funct
op
rs
rt
offset
REGIMM
rs
sub
offset
SPECIAL
rs
rt
rd
sa
funct
Instructions
Description
Format
Multiplication/division instruction (1)
DMULT
DMULTU
DDIV
DDIVU
Multiplication/division instruction (2)
MADD16
DMADD16
Branch instruction (1)
BEQL
BNEL
BLEZL
BGTZL
Branch instruction (2)
BLTZL
BGEZL
BLTZALL
BGEZALL
Exception instruction
TGE
TGEU
TLT
TLTU
TEQ
TNE
Exception immediate instruction
TGEI
TGEIU
TLTI
TLTIU
TEQI
TNEI
op
rs
rt
rd
sa
funct
Doubleword Multiply
Doubleword Multiply Unsigned
Doubleword Divide
Doubleword Divide Unsigned
Multiply and Add 16-bit Integer
Doubleword Multiply and Add 16-bit Integer
Branch On Equal Likely
Branch On Not Equal Likely
Branch On Less Than Or Equal To Zero Likely
Branch On Greatrer Than Zero Likely
Branch On Less Than Zero Likely
Branch On Greater Than Or Equal To Zero Likely
Branch On Less Than Zero And Link Likely
Branch On Greater Than Or Equal To Zero And Link Likely
Trap If Greater Than Or Equal
Trap If Greater Than Or Equal Unsigned
Trap If Less Than
Trap If Less Than Unsigned
Trap If Equal
Trap If Not Equal
Trap If Greater Than Or Equal Immediate
Trap If Greater Than Or Equal Immediate Unsigned
Trap If Less Than Immediate
Trap If Less Than Immediate Unsigned
Trap If Equal Immediate
Trap If Not Equal Immediate
DMULT
DMULTU
DDIV
DDIVU
MADD16
DMADD16
BEQL
BNEL
BLEZL
BGTZL
BLTZL
BGEZL
BLTZALL
BGEZALL
TGE
TGEU
TLT
TLTU
TEQ
TNE
TGEI
TGEIU
TLTI
TLTIU
TEQI
TNEI
rs, rt
rs, rt
rs, rt
rs, rt
rs, rt
rs, rt
rs, rt, offset
rs, rt, offset
rs, offset
rs, offset
rs, offset
rs, offset
rs, offset
rs, offset
rs, rt
rs, rt
rs, rt
rs, rt
rs, rt
rs, rt
rs, immediate
rs, immediate
rs, immediate
rs, immediate
rs, immediate
rs, immediate