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參數(shù)資料
型號： XRT91L80IB
廠商： Exar Corporation
文件頁數(shù)： 43/46頁
文件大?。?/td> 0K
描述： IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告： XRT91L80IB Obsolescence 6/Sept/2010
標準包裝： 126
類型： 收發(fā)器
規(guī)程： SONET/SDH
電源電壓： 3.3V
安裝類型： 表面貼裝
封裝/外殼： 196-LFBGA
供應商設備封裝： 196-STBGA（12x12）
包裝： 托盤
XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
4
PIN DESCRIPTIONS
SERIAL MICROPROCESSOR INTERFACE
NAME
LEVEL
TYPE
PIN
DESCRIPTION
HOST/HW
LVTTL,
LVCMOS
I
C9
Host or Hardware Mode Select Input
The XRT91L80 offers two modes of operation for interfacing to the
device. The Host mode uses a serial microprocessor interface for
programming individual registers. The Hardware mode is controlled
by the state of the hardware pins set by the user. When left uncon-
nected, by default, the device is configured in the Hardware mode.
"Low" = Hardware Mode
"High" = Host Mode
This pin is provided with an internal pull-down.
CS
LVTTL,
LVCMOS
I
A10
Chip Select Input (Host Mode Only)
Active "Low" signal. This signal enables the serial microprocessor
interface by pulling chip select "Low". The serial microprocessor is
disabled when the chip select signal returns "High".
NOTE: The serial microprocessor interface does not support burst
mode. Chip Select must be de-asserted after each
operation cycle.
This pin is provided with an internal pull-up.
SCLK
LVTTL,
LVCMOS
I
B9
Serial Clock Input (Host Mode Only)
Once CS is pulled "Low", the serial microprocessor interface
requires 16 clock cycles for a complete Read or Write operation.
This pin is provided with an internal pull-down.
SDI
LVTTL,
LVCMOS
I
A9
Serial Data Input (Host Mode Only)
When CS is pulled "Low", the serial data input is sampled on the ris-
ing edge of SCLK.
This pin is provided with an internal pull-down.
SDO
LVCMOS
O
C8
Serial Data Output (Host Mode Only)
If a Read function is initiated, the serial data output is updated on
the falling edge of SCLK8 through SCLK15, with the LSB (D0)
updated first. This enables the data to be sampled on the rising
edge of SCLK9 through SCLK16.
INT
LVCMOS
O
C11
Interrupt Output (Host Mode Only)
Active "Low" signal. This signal is asserted "Low" when a change in
alarm status occurs. Once the status registers have been read, the
interrupt pin will return "High".
NOTE: This pin requires an external pull-up resistor.
RESET
LVTTL,
LVCMOS
I
B10
Master Reset Input
Active "Low" signal. When this pin is pulled "Low" for more than
10
S, the internal registers are set to their default state. See the
register description for the default values.
This pin is provided with an internal pull-up.
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相關代理商/技術參數(shù)
參數(shù)描述
XRT91L80IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
XRT91L81 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82ES 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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