REVISION
參數(shù)資料
型號: XRT91L80IB
廠商: Exar Corporation
文件頁數(shù): 40/46頁
文件大?。?/td> 0K
描述: IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告: XRT91L80IB Obsolescence 6/Sept/2010
標準包裝: 126
類型: 收發(fā)器
規(guī)程: SONET/SDH
電源電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 196-LFBGA
供應商設備封裝: 196-STBGA(12x12)
包裝: 托盤
XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
42
REVISION HISTORY
REVISION #
DATE
DESCRIPTION
P1.0.0
October 2004
1st release of the XRT91L80 product brief
P1.0.1
October 2004
Fixed typos throughout document
P1.0.2
October 2004
Fixed typos throughout document
P1.0.3
January 2005
Added jitter transfer and tolerance mask test results and phase noise transmit jitter
generation results, added CS de-assertion note on section 5.1, fixed register 0x02,
0x04, 0x05 microprocessor bit descriptions, updated pin descriptions, corrected ’fall-
ing edge’ typo in section 3.6 to ’rising edge’, and enhanced receive and transmit
interface block diagrams.
P1.0.4
March 2005
Remove ’RXSEL’ reference on the RXIP/N pin description. Minor edit in receive sec-
tion 2.0. FIFO_RST corrected for active High in section 3.4. Removed unsupported
note for transparent mode FIFO operation in section 3.3.
P1.0.5
April 2005
1.Design change: Renamed DISRD, TRIRXD, and TRITXCLKO16P/N to LOSD-
MUTE, DISRD, and TXCLKO16DIS respectively. Corrected and redefined pin defini-
tions for LOSDMUTE, DISRD, and TXCLKO16DIS.
2.Renamed LOSEXT, REFFREQSEL, TXCLKIP/N, RXCLKP/N, RXD[3:0]P/N,
RXCLK16P/N, LPTIME_JA, LPTIME_NO_JA, RXP/N to SDEXT, ALTFREQSEL,
TXPCLKIP/N, RXPCLKOP/N, RXDO[3:0]P/N, RXCLKO16P/N, LOOPTM_JA,
LOOPTM_NOJA, XRES1P/N respectively.
3.Updated STBGA pinout names to include above mentioned changes.
4.Corrected LOOPBW and RLOOPP pin descriptions.
5.Corrected RXDO[3:0]P/N description error from ’updated on rising edge’ to
’updated on falling edge’ of RXPCLKOP/N.
5.Updated and improved all pin list decriptions and formatted table headers.
6.Added JTAG input pin pull-up and pull-down descriptions.
7.Removed unsupported note for transparent mode FIFO operation in section 3.3
and enhanced and corrected FIFO reset operation description.
8.Moved FIFO Figure 11 from sect 3.6 to section 3.3.
9.Corrected Figure 13, “Loop Timing Mode Using an External Cleanup VCXO.
10.Corrected Loopback definition errors in Section 4.0.
11.Significantly enhanced Sec. 2.3 "LOS" to "External Signal Detection, Sec. 3.3
Transmit FIFO, and Sec. 3.6 CMU and Retimer, and Sec. 3.7 Loop timing and Clock
Control.
12.Enhanced Transmit/Receive Parallel Data and Clock Input/Output timing diagram
and tables.
13.Added CMU and CDR performace tables.
14.Added CML input swing characteristics table.
15.Added LOSD declaration polarity setting tables.
16.Added LVDS biasing resistor diagram.
17.Reformatted and Enhanced AC/DC electrical characteristics tables.
18.Change MHz to Mbps to reflect Parallel data I/O and Serial I/O more accurately.
Corrected and enhanced PISO and SIPO diagrams.
19.Removed all reference to "differential limiting amplifier" and TXO2P/N pins.
20.Updated Microprocessor Register Bits and Descriptions to reflect changes.
21.Added Microprocessor Register Names.
22.Retouched 91L80 Block Diagram.
23.Changed OC-48 name to STS-48.
24.Minor edits and spelling and grammatical corrections.
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