參數(shù)資料
型號(hào): XRT91L80IB
廠商: Exar Corporation
文件頁(yè)數(shù): 4/46頁(yè)
文件大小: 0K
描述: IC TXRX SONET/SDH 4BIT 196STBGA
產(chǎn)品變化通告: XRT91L80IB Obsolescence 6/Sept/2010
標(biāo)準(zhǔn)包裝: 126
類(lèi)型: 收發(fā)器
規(guī)程: SONET/SDH
電源電壓: 3.3V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 196-LFBGA
供應(yīng)商設(shè)備封裝: 196-STBGA(12x12)
包裝: 托盤(pán)
XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
10
POLARITY
LVTTL,
LVCMOS
I
C4
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"Low" = SDEXT is active "Low."
"High" = SDEXT is active "High."
This pin is provided with an internal pull-down.
LOSDET
LVCMOS
O
C5
LOS Detect Condition
Flags LOSD condition based on SDEXT signal coming from the
optical module.
"Low" = No Alarm
"High" = A LOS condition is present
LOSDMUTE
LVTTL,
LVCMOS
I
A3
Parallel Receive Data Output Mute Upon LOSD
If this pin is asserted "High", the receive data output will auto-
matically be forced to a logic state of "0" when an LOSD condi-
tion occurs.
"Low" = Disabled
"High" = Mute RXDO[3:0]P/N Data Upon LOSD Condition
This pin is provided with an internal pull-down.
POWER AND GROUND
NAME
TYPE
PIN
DESCRIPTION
VDD3.3
PWR
A8, D9, D10, D11, E11,
P13, P14
CMOS Digital 3.3V I/O Power Supply
VDD3.3 should be isolated from the analog power supplies. For
best results, use a ferrite bead along with an internal power plane
separation. The VDD3.3 power supply pins should have bypass
capacitors to the nearest ground.
AVDD3.3_RX
PWR
D3, E3
Analog 3.3V I/O Receiver Power Supply
AVDD3.3_RX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_RX power supply pins should
have bypass capacitors to the nearest ground.
AVDD3.3_TX
PWR
P5, P9
Analog 3.3V I/O Transmitter Power Supply
AVDD3.3_TX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD3.3_TX power supply pins should
have bypass capacitors to the nearest ground.
VDD1.8
PWR
A13, B7, B13, D12, E12,
K11, L9, L10, M9, M10,
M11
CMOS Digital 1.8V Core Power Supply
VDD1.8 should be isolated from the analog power supplies. For
best results, use a ferrite bead along with an internal power plane
separation. The VDD1.8 power supply pins should have bypass
capacitors to the nearest ground.
AVDD1.8_RX
PWR
D4, D5, D6, D8, F3, G3
Analog 1.8V Core Receiver Power Supply
AVDD1.8_RX should be isolated from the digital power supplies.
For best results, use a ferrite bead along with an internal power
plane separation. The AVDD1.8_RX power supply pins should
have bypass capacitors to the nearest ground.
RECEIVER SECTION
NAME
LEVEL
TYPE
PIN
DESCRIPTION
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