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參數(shù)資料
| 型號(hào)： | XRT91L80IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 33/46頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 產(chǎn)品變化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 196-STBGA（12x12） |
| 包裝： | 托盤 |
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XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
36
D5
Reserved
This Register Bit is Not Used
X
D4
Reserved
This Register Bit is Not Used
X
D3
Reserved
This Register Bit is Not Used
X
D2
DLOOP
Digital Local Loopback
Digital local loopback allows the transmit input pins to be looped
back to the receive output pins for local diagnostics. The transmit
serial data output is valid during the digital loopback.
"0" = Disabled
"1" = Enable Digital Local Loopback
NOTE: DLOOP and RLOOPS can be enabled simultaneously to
achieve a dual loopback diagnostic feature.
R/W
0
D1
RLOOPS
Serial Remote Loopback
Serial remote loopback allows the receive serial input pins to be
looped back to the transmit serial output pins for remote diagnos-
tics. The receive data output is valid during a serial remote loop-
back.
"0" = Disabled
"1" = Enable Remote Serial Loopback
NOTE: DLOOP and RLOOPS can be enabled simultaneously to
achieve a dual loopback diagnostic feature.
R/W
0
D0
RLOOPP
Parallel Remote Loopback
Parallel remote loopback has the same affect as the serial remote
loopback, except that the data input is allowed to pass through the
SIPO before it’s looped back to the transmit path, wherein it
passes through the transmit FIFO, through the PISO, and back out
the transmit serial output. The receive data output is valid during a
parallel remote loopback.
"0" = Disabled
"1" = Enable Remote Parallel Loopback
NOTE: DLOOP and RLOOPS should be disabled when RLOOPP
is enabled. The internal FIFO should also be flushed using
FIFO_RST when parallel remote loopback is enabled/
disabled.
R/W
0
DIAGNOSTIC CONTROL REGISTER (0X05H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
相關(guān)PDF資料 |
PDF描述 |
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| V24B48M150BG2 | CONVERTER MOD DC/DC 48V 150W |
| VI-J52-MX-F1 | CONVERTER MOD DC/DC 15V 75W |
| V24B48M150BF2 | CONVERTER MOD DC/DC 48V 150W |
| VI-J51-MX-F4 | CONVERTER MOD DC/DC 12V 75W |
| V24B36M150BL | CONVERTER MOD DC/DC 36V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L80IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L81 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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