
XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
32
TABLE 13: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION
TABLE 12: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION
INTERRUPT STATUS CONTROL REGISTER (0X01H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
D6
Reserved
This Register Bit is Not Used
X
D5
Reserved
This Register Bit is Not Used
X
D4
VCXOIS
Voltage Controlled External Oscillator Lock Interrupt Status
An external interrupt will not occur unless the VCXOIE is set to "1"
in the channel register 0x00h.
"0" = No Change
"1" = Change in VCXO Lock Status Occurred
NOTE: VCXOLKEN must be enabled for this bit to have functional
meaning.
RUR
0
D3
LOSIS
Loss of Signal Interrupt Status
An external interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0x00h.
"0" = No Change
"1" = Change in LOS Status Occurred
RUR
0
D2
CDRIS
Clock and Data Recovery Lock Interrupt Status
An external interrupt will not occur unless the CDRIE is set to "1" in
the channel register 0x00h.
"0" = No Change
"1" = Change in CDR Lock Status Occurred
RUR
0
D1
CMUIS
Clock Multiplier Unit Lock Interrupt Status
An external interrupt will not occur unless the CMUIE is set to "1" in
the channel register 0x00h.
"0" = No Change
"1" = Change in CMU Lock Status Occurred
RUR
0
D0
FIFOIS
FIFO Overflow Interrupt Status
An external interrupt will not occur unless the FIFOIE is set to "1" in
the channel register 0x00h.
"0" = No Change
"1" = Change in FIFO Overflow Status Occurred
RUR
0
STATUS CONTROL REGISTER (0X02H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Register Bit is Not Used
X
D6
Reserved
This Register Bit is Not Used
X