- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9687 > XRT91L80IB (Exar Corporation)IC TXRX SONET/SDH 4BIT 196STBGA PDF資料下載
參數(shù)資料
| 型號： | XRT91L80IB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 27/46頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH 4BIT 196STBGA |
| 產(chǎn)品變化通告： | XRT91L80IB Obsolescence 6/Sept/2010 |
| 標準包裝： | 126 |
| 類型： | 收發(fā)器 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 3.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 196-STBGA（12x12） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
XRT91L80
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
REV. 1.0.0
30
5.2
16-BIT SERIAL DATA INPUT DESCRITPTION
The serial data input is sampled on the rising edge of SCLK. In readback mode, the serial data output is
updated on the falling edge of SCLK. The serial data must be applied to the transceiver LSB first. The 16 bits
of serial data are described below.
5.2.1
R/W (SCLK1)
The first serial bit applied to the transceiver informs the microprocessor that a Read or Write operation is
desired. If the R/W bit is set to “0”, the microprocessor is configured for a Write operation. If the R/W bit is set
to “1”, the microprocessor is configured for a Read operation.
5.2.2
A[5:0] (SCLK2 - SCLK7)
The next 6 SCLK cycles are used to provide the address to which a Read or Write operation will occur. A0
(LSB) must be sent to the transceiver first followed by A1 and so forth until all 6 address bits have been
sampled by SCLK.
5.2.3
X (Dummy Bit SCLK8)
The dummy bit sampled by SCLK8 is used to allow sufficient time for the serial data output pin to update data
if the readback mode is selected by setting R/W = “1”. Therefore, the state of this bit is ignored and can hold
either “0” or “1” during both Read and Write operations.
5.2.4
D[7:0] (SCLK9 - SCLK16)
The next 8 SCLK cycles are used to provide the data to be written into the internal register chosen by the ad-
dress bits. D0 (LSB) must be sent to the transceiver first followed by D1 and so forth until all 8 data bits have
been sampled by SCLK. Once 16 SCLK cycles have been complete, the transceiver holds the data until CS is
pulled “High” whereby, the serial microprocessor latches the data into the selected internal register.
5.3
8-BIT SERIAL DATA OUTPUT DESCRIPTION
The serial data output is updated on the falling edge of SCLK9 - SCLK16 if R/W is set to “1”. D0 (LSB) is pro-
vided on SCLK9 to the SDO pin first followed by D1 and so forth until all 8 data bits have been updated. The
SDO pin allows the user to read the contents stored in individual registers by providing the desired address on
the SDI pin during the Read cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V24B48M150BG2 | CONVERTER MOD DC/DC 48V 150W |
| VI-J52-MX-F1 | CONVERTER MOD DC/DC 15V 75W |
| V24B48M150BF2 | CONVERTER MOD DC/DC 48V 150W |
| VI-J51-MX-F4 | CONVERTER MOD DC/DC 12V 75W |
| V24B36M150BL | CONVERTER MOD DC/DC 36V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT91L80IB-F | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| XRT91L81 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L81IB | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER |
| XRT91L82ES | 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。