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參數(shù)資料
| 型號(hào)： | XRT86L30IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | DATACOM, FRAMER, PQFP128 |
| 封裝： | 14 X 20 MM, 1.4 MM HEIGHT, TQFP-128 |
| 文件頁數(shù)： | 8/284頁 |
| 文件大小： | 4058K |
| 代理商： | XRT86L30IB |
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XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
PRELIMINARY
REV. P1.0.1
A
LIST OF FIGURES
Figure 1.: XRT86L30 1-channel DS1 (T1/E1/J1) Framer/LIU Combo ...............................................................................1
Figure 2.: Simplified Block Diagram of the Microprocessor Interface Block ....................................................................24
Figure 3.:
Intel μP Interface Signals During Programmed I/O Read and Write Operations .............................................28
Figure 4.: Motorola μP Interface Signals During Programmed I/O Read and Write Operations ......................................30
Figure 5.: Motorola 68K μP Interface Signals During Programmed I/O Read and Write Operations ..............................31
Figure 6.: DMA Mode for the XRT86L30 and a Microprocessor ......................................................................................32
Figure 7.: LIU Transmit Connection Diagram Using Internal Termination .....................................................................149
Figure 8.: LIU Receive Connection Diagram Using Internal Termination .....................................................................149
Figure 9.: Simplified Block Diagram of the Transmit Interface for 1:1 and 1+1 Redundancy ........................................150
Figure 10.: Simplified Block Diagram of the Receive Interface for 1:1 and 1+1 Redundancy .......................................151
Figure 11.: Simplified Block Diagram of a Non-Intrusive Monitoring Application ...........................................................152
Figure 12.: Transmit T1/E1 Serial PCM Interface ..........................................................................................................153
Figure 13.: Receive T1/E1 Serial PCM Interface ...........................................................................................................153
Figure 14.: T1 Fractional Interface .................................................................................................................................154
Figure 15.: T1/E1 Time Slot Substitution and Control ....................................................................................................155
Figure 16.: Robbed Bit Signaling / CAS Signaling .........................................................................................................156
Figure 17.: ESF / CAS External Signaling Bus ..............................................................................................................156
Figure 18.: SF / SLC-96 or 4-code Signaling in ESF / CAS External Signaling Bus ......................................................157
Figure 19.: T1/E1 Overhead Interface ...........................................................................................................................158
Figure 20.: T1 External Overhead Datalink Bus ............................................................................................................158
Figure 21.: E1 Overhead External Datalink Bus ............................................................................................................159
Figure 22.: Simplified Block Diagram of the Framer Bypass Mode ...............................................................................159
Figure 23.: T1 High-Speed Non-Multiplexed Interface ...................................................................................................160
Figure 24.: E1 High-Speed Non-Multiplexed Interface ..................................................................................................160
Figure 25.: Transmit High-Speed Bit Multiplexed Block Diagram ..................................................................................161
Figure 26.: Receive High-Speed Bit Multiplexed Block Diagram ...................................................................................161
Figure 27.: Simplified Block Diagram of Local Analog Loopback ..................................................................................162
Figure 28.: Simplified Block Diagram of Remote Loopback ...........................................................................................162
Figure 29.: Simplified Block Diagram of Digital Loopback .............................................................................................163
Figure 30.: Simplified Block Diagram of Dual Loopback ................................................................................................163
Figure 31.: Simplified Block Diagram of the Framer Remote Line Loopback ................................................................163
Figure 32.: Simplified Block Diagram of the Framer Local Loopback ............................................................................164
Figure 33.: Simplified Block Diagram of the Framer Local Loopback ............................................................................164
Figure 34.: HDLC Controllers .........................................................................................................................................165
Figure 35.: LAPD Frame Structure ................................................................................................................................168
Figure 36.: Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86L30 .......................................175
Figure 37.: DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode ..........................................177
Figure 38.: DS1 Transmit Overhead Input Timing in N or SLC96 Framing Format Mode ..........................................178
Figure 39.: DS1 Transmit Overhead Input Interface module in T1DM Framing Format mode ......................................178
Figure 40.: Block Diagram of the DS1 Receive Overhead Output Interface of XRT86L30 ............................................179
Figure 41.: DS1 Receive Overhead Output Interface module in ESF framing format mode .........................................180
Figure 42.: DS1 Receive Overhead Output Interface Timing in N or SLC96 Framing Format mode ..........................181
Figure 43.: DS1 Receive Overhead Output Interface Timing in T1DM Framing Format mode .....................................182
Figure 44.: Block Diagram of the E1 Transmit Overhead Input Interface of XRT86L30 ................................................183
Figure 45.: E1 Transmit Overhead Input Interface Timing .............................................................................................185
Figure 46.: Block Diagram of the E1 Receive Overhead Output Interface of XRT86L30 ..............................................185
Figure 47.: E1 Receive Overhead Output Interface Timing ...........................................................................................187
Figure 48.: TAOS (Transmit All Ones) ...........................................................................................................................188
Figure 49.: Simplified Block Diagram of the ATAOS Function .......................................................................................189
Figure 50.: Network Loop Up Code Generation .............................................................................................................189
Figure 51.: Network Loop Down Code Generation ........................................................................................................189
Figure 52.: Long Haul Line Build Out with -7.5dB Attenuation .......................................................................................190
Figure 53.: Long Haul Line Build Out with -15dB Attenuation ........................................................................................190
Figure 54.: Long Haul Line Build Out with -22.5dB Attenuation .....................................................................................191
Figure 55.: Arbitrary Pulse Segment Assignment ..........................................................................................................192
Figure 56.: Typical Connection Diagram Using Internal Termination ............................................................................193
Figure 57.: Typical Connection Diagram Using Internal Termination ...........................................................................194
Figure 58.: Typical Connection Diagram Using One External Fixed Resistor ...............................................................195
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86SH221 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH221IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH328 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH328_07 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86SH328IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86L30IV | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86L30IV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86L32IB | 制造商:Exar Corporation 功能描述: |
| XRT86SH221 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU |
| XRT86SH221_08 | 制造商:EXAR 制造商全稱:EXAR 功能描述:SDH-TO-PDH FRAMER/MAPPER WITH INTEGRATED 21-CHANNEL E1 SH LIU |
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