
XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
PRELIMINARY
3.0
MICROPROCESSOR INTERFACE BLOCK
The Microprocessor Interface section supports communication between the local microprocessor (μP) and the
Framer/LIU combo. The XRT86L30 supports an Intel asynchronous interface, Motorola 68K asynchronous,
and a Motorola Power PC interface. The microprocessor interface is selected by the state of the PTYPE[2:0]
input pins. Selecting the microprocessor interface is shown in Table 2.
REV. P1.0.1
24
The XRT86L30 uses multipurpose pins to configure the device appropriately. The local μP configures the
Framer/LIU by writing data into specific addressable, on-chip Read/Write registers. The microprocessor inter-
face provides the signals which are required for a general purpose microprocessor to read or write data into
these registers. The microprocessor interface also supports polled and interrupt driven environments. A sim-
plified block diagram of the microprocessor is shown in Figure 2.
3.0.1
The
XRT86L30
may be configured into different operating modes and have its performance monitored by soft-
ware through a standard microprocessor using data, address and control signals. These interface signals are
described below in Table 3, Table 4, and Table 5. The microprocessor interface can be configured to operate in
Intel mode or Motorola mode. When the microprocessor interface is operating in Intel mode, some of the con-
trol signals function in a manner required by the Intel 80xx family of microprocessors. Likewise, when the mi-
croprocessor interface is operating in Motorola mode, then these control signals function in a manner as re-
quired by the Motorola Power PC family of microprocessors. (For using a Motorola 68K asynchronous proces-
sor, see Figure 5 and Table 8) Table 3 lists and describes those microprocessor interface signals whose role is
constant across the two modes. Table 4 describes the role of some of these signals when the microprocessor
interface is operating in the Intel mode. Likewise, Table 5 describes the role of these signals when the micro-
processor interface is operating in the Motorola mode.
The Microprocessor Interface Block Signals
T
ABLE
2: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
PTYPE[2:0]
M
ICROPROCESSOR
M
ODE
0h (000)
Intel 68HC11, 8051, 80C188
(Asynchronous)
1h (001)
Motorola 68K (Asynchronous)
7h (111)
Motorola MPC8260, MPC860
Power PC (Synchronous)
F
IGURE
2. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
μ
Processor
Interface
WR
RD
ALE
PTYPE [2:0]
Reset
DBEN
BLAST
ACK[1:0]
PCLK
CS
ADDR[11:0]
DATA[7:0]
RDY
INT
REQ[1:0]