參數(shù)資料
型號: XRT83VSH314IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA304
封裝: 31 X 31 MM, 1.27 MM PITCH, PLASTIC, BGA-304
文件頁數(shù): 74/80頁
文件大小: 497K
代理商: XRT83VSH314IB
XRT83VSH314
71
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
T
ABLE
53: E1 A
RBITRARY
S
ELECT
E1 A
RBITRARY
S
ELECT
R
EGISTER
(0
X
F4
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D[7:1]
Reserved
D0
E1Arben
E1 Arbitrary Pulse Enable
This bit is used to enable the Arbitrary Pulse Generators for shap-
ing the transmit pulse shape when E1 mode is selected. If this bit
is set to "1", all 14 channels will be configured for the Arbitrary
Mode. However, each channel is individually controlled by pro-
gramming the channel registers 0xn8 through 0xnF, where n is the
number of the channel.
"0" = Disabled (Normal E1 Pulse Shape ITU G.703)
"1" = Arbitrary Pulse Enabled
R/W
0
T
ABLE
54: M
ICROPROCESSOR
R
EGISTER
0
X
FE
H
B
IT
D
ESCRIPTION
D
EVICE
"ID" R
EGISTER
(0
X
FE
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Device "ID" The device "ID" of the XRT83VSH314 short haul LIU is 0xF2h.
Along with the revision "ID", the device "ID" is used to enable soft-
ware to identify the silicon adding flexibility for system control and
debug.
RO
1
1
1
1
0
0
1
0
T
ABLE
55: M
ICROPROCESSOR
R
EGISTER
0
X
FF
H
B
IT
D
ESCRIPTION
R
EVISION
"ID" R
EGISTER
(0
X
FF
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Revision
"ID"
The revision "ID" of the XRT83VSH314 LIU is used to enable soft-
ware to identify which revision of silicon is currently being tested.
The revision "ID" for the first revision of silicon will be 0x01h.
N
OTE
:
The value contained in this register is subject to change
when a newer revision of the silicon has been issued.
RO
0
0
0
0
0
0
0
1
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