參數(shù)資料
型號(hào)： XRT83VSH314IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA304
封裝： 31 X 31 MM, 1.27 MM PITCH, PLASTIC, BGA-304
文件頁(yè)數(shù)： 70/80頁(yè)
文件大?。?/td> 497K
代理商： XRT83VSH314IB
XRT83VSH314
67
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.1
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits in
register 0xE9h. Therefore, if the clock selection bits are being programmed, the frequency of the PLL output
will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within
the same register while selecting the input/output clock frequency. For best results, register 0xE9h can be
broken down into two sub-registers with the MSB being bit D4 and the LSB being bits D[3:0] as shown in
Figure 36
.
N
OTE
:
Bits D[7:5] are reserved.
F
IGURE
36. R
EGISTER
0
X
E9
H
S
UB
R
EGISTERS
Programming Examples:
Example 1
: Changing bits D[7:4]
If bit D4 is the only values within the register that will change in a WRITE process, the microprocessor only
needs to initiate ONE write operation.
Example 2
: Changing bits D[3:0]
If bits D[3:0] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 3
: Changing bits within the MSB and LSB
In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE
write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can
either change the clock selection bits D[3:0] (LSB) and then change bit D4 (MSB) on the SECOND write, or
vice-versa. No order or sequence is necessary.
T
ABLE
48: M
ICROPROCESSOR
R
EGISTER
0
X
E8
H
B
IT
D
ESCRIPTION
G
LOBAL
R
EGISTER
(0
X
E8
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
LCVCNT7
LCVCNT6
LCVCNT5
LCVCNT4
LCVCNT3
LCVCNT2
LCVCNT1
LCVCNT0
Line Code Violation Byte Contents
These bits contain the LCV counter contents of the Byte selected
by bit D2 in register 0xE6h for a given channel. The channel is
addressed by using bits D[3:0] in register 0xE5h. By default, the
contents contain the LSB, however no channel is selected..
R/W
0
0
0
0
0
0
0
0
D0
D1
D2
D3
D4
D5
D6
D7
MSB
LSB
Clock Selection Bits
Reserved, TCLKCNTL
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83VSH314IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 14 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH314IB-SAM 制造商:Exar Corporation 功能描述:FOR FUJITSU ONLY
XRT83VSH316 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316_07 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316ES 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 16 CH T1/E1LIUSH LOW COST VERSION RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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