參數(shù)資料
型號: XRT83VSH314IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA304
封裝: 31 X 31 MM, 1.27 MM PITCH, PLASTIC, BGA-304
文件頁數(shù): 21/80頁
文件大小: 497K
代理商: XRT83VSH314IB
XRT83VSH314
18
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
3.2
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an
incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered
data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To
update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register.
Figure 5
is a
timing diagram of the receive data updated on the rising edge of RCLK.
Figure 6
is a timing diagram of the
receive data updated on the falling edge of RCLK. The timing specifications are shown in
Table 4
.
Clock and Data Recovery
T
ABLE
3: R
ECEIVE
T
ERMINATIONS
RXTSEL
TERSEL1
TERSEL0
RXRES1
RXRES0
R
ext
R
int
M
ODE
0
x
x
x
x
R
ext
T1/E1/J1
1
0
0
0
0
100
T1
1
0
1
0
0
110
J1
1
1
0
0
0
75
E1
1
1
1
0
0
120
E1
1
0
0
0
1
240
172
T1
1
0
1
0
1
240
204
J1
1
1
0
0
1
240
108
E1
1
1
1
0
1
240
240
E1
1
0
0
1
0
210
192
T1
1
0
1
1
0
210
232
J1
1
1
0
1
0
210
116
E1
1
1
1
1
0
210
280
E1
1
0
0
1
1
150
300
T1
1
0
1
1
1
150
412
J1
1
1
0
1
1
150
150
E1
1
1
1
1
1
150
600
E1
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相關代理商/技術參數(shù)
參數(shù)描述
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