參數(shù)資料
型號(hào)： XRT83VSH314IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA304
封裝： 31 X 31 MM, 1.27 MM PITCH, PLASTIC, BGA-304
文件頁(yè)數(shù)： 5/80頁(yè)
文件大?。?/td> 497K
代理商： XRT83VSH314IB
XRT83VSH314
II
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
4.5.2 QRSS/PRBS GENERATION....................................................................................................................................... 28
T
ABLE
9: R
ANDOM
B
IT
S
EQUENCE
P
OLYNOMIALS
........................................................................................................................... 28
4.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 28
4.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 28
T
ABLE
10: S
HORT
H
AUL
L
INE
B
UILD
O
UT
....................................................................................................................................... 28
4.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 29
F
IGURE
18. A
RBITRARY
P
ULSE
S
EGMENT
A
SSIGNMENT
.................................................................................................................. 29
4.6.3 SETTING REGISTERS TO SELECT AN ARIBTRARY PULSE................................................................................. 29
T
ABLE
11: T
YPICAL
ROM V
ALUES
.................................................................................................................................................. 30
4.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 30
4.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 30
F
IGURE
19. T
YPICAL
C
ONNECTION
D
IAGRAM
U
SING
I
NTERNAL
T
ERMINATION
................................................................................... 30
5.0 T1/E1 APPLICATIONS ........................................................................................................................31
5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 31
5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 31
F
IGURE
20. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
L
OCAL
A
NALOG
L
OOPBACK
......................................................................................... 31
5.1.2 REMOTE LOOPBACK................................................................................................................................................ 31
F
IGURE
21. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
R
EMOTE
L
OOPBACK
.................................................................................................... 31
5.1.3 DIGITAL LOOPBACK................................................................................................................................................. 32
F
IGURE
22. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
IGITAL
L
OOPBACK
..................................................................................................... 32
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 32
F
IGURE
23. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
D
UAL
L
OOPBACK
........................................................................................................ 32
5.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 33
F
IGURE
24. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
AN
84-C
HANNEL
A
PPLICATION
..................................................................................... 33
T
ABLE
12: C
HIP
S
ELECT
A
SSIGNMENTS
.......................................................................................................................................... 33
5.3 LINE CARD REDUNDANCY .......................................................................................................................... 34
5.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS.................................................................................................... 34
5.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY.................................................................................. 34
F
IGURE
25. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
......................................... 34
5.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 34
F
IGURE
26. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
1:1
AND
1+1 R
EDUNDANCY
........................................... 35
5.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 35
5.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36
F
IGURE
27. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
I
NTERFACE
FOR
N+1 R
EDUNDANCY
...................................................... 36
5.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY................................................................................................... 37
F
IGURE
28. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
I
NTERFACE
FOR
N+1 R
EDUNDANCY
........................................................ 37
5.4 POWER FAILURE PROTECTION .................................................................................................................. 38
5.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38
5.6 NON-INTRUSIVE MONITORING .................................................................................................................... 38
F
IGURE
29. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
A
N
ON
-I
NTRUSIVE
M
ONITORING
A
PPLICATION
.............................................................. 38
5.7 ANALOG BOARD CONTINUITY CHECK ...................................................................................................... 39
F
IGURE
30. ATP
TESTING
BLOCK
DIAGRAM
..................................................................................................................................... 39
F
IGURE
31. T
IMING
D
IAGRAM
FOR
ATP T
ESTING
........................................................................................................................... 39
5.7.1 TRANSMITTER TTIP AND TRING TESTING............................................................................................................. 39
5.7.2 RECEIVER RTIP AND RRING.................................................................................................................................... 40
6.0 MICROPROCESSOR INTERFACE BLOCK .......................................................................................41
T
ABLE
13: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
................................................................................................... 41
F
IGURE
32. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
.................................................................. 41
6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 42
T
ABLE
14: XRT84SH314S M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
COMMON
TO
BOTH
I
NTEL
AND
M
OTOROLA
M
ODES
.................... 42
T
ABLE
15: I
NTEL
MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
.................................................................................................... 42
T
ABLE
16: M
OTOROLA
M
ODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
........................................................................................... 43
6.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .............................................................. 44
F
IGURE
33. I
NTEL
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
............................................ 45
T
ABLE
17: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
........................................................................................ 45
6.3 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 46
F
IGURE
34. M
OTOROLA
MPC86X μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................... 47
T
ABLE
18: M
OTOROLA
MPC86X M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
................................................................ 47
F
IGURE
35. M
OTOROLA
68K μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
............................ 48
T
ABLE
19: M
OTOROLA
68K M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
........................................................................ 48
7.0 REGISTER DESCRIPTIONS ...............................................................................................................49
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
(ADDR[7:0]) ................................................................................................... 49
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
C
HANNEL
D
ESCRIPTION
................................................................................................... 49
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
G
LOBAL
D
ESCRIPTION
..................................................................................................... 50
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參數(shù)描述
XRT83VSH314IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 14 Channel Short-Haul RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT83VSH314IB-SAM 制造商:Exar Corporation 功能描述:FOR FUJITSU ONLY
XRT83VSH316 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316_07 制造商:EXAR 制造商全稱:EXAR 功能描述:16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83VSH316ES 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 16 CH T1/E1LIUSH LOW COST VERSION RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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