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參數(shù)資料
| 型號(hào)： | XRT83L34 |
| 廠商： | Exar Corporation |
| 英文描述： | QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | 四T1/E1/J1收發(fā)左/上海收發(fā)器和時(shí)鐘恢復(fù)和抖動(dòng)衰減器 |
| 文件頁數(shù)： | 65/82頁 |
| 文件大?。?/td> | 447K |
| 代理商： | XRT83L34 |
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XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
62
T
ABLE
35: M
ICROPROCESSOR
R
EGISTER
#64, B
IT
D
ESCRIPTION
R
EGISTER
A
DDRESS
1000000
N
AME
F
UNCTION
R
EGISTER
T
YPE
R
ESET
V
ALUE
B
IT
#
D7
SR/DR
Single-rail/Dual-rail Select:
Writing a “1” to this bit configures
all 8 channels in the XRT83L34 to operate in the Single-rail
mode.
Writing a “0” configures the XRT83L34 to operate in Dual-rail
mode.
R/W
0
D6
ATAOS
Automatic Transmit All Ones Upon RLOS:
Writing a “1” to
this bit enables the automatic transmission of All "Ones" data
to the line for the channel that detects an RLOS condition.
Writing a “0” disables this feature.
R/W
0
D5
RCLKE
Receive Clock Edge:
Writing a “1” to this bit selects receive
output data of all channels to be updated on the negative edge
of RCLK.
Wring a “0” selects data to be updated on the positive edge of
RCLK.
R/W
0
D4
TCLKE
Transmit Clock Edge:
Writing a “0” to this bit selects transmit
data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all
channels to be sampled on the falling edge of TCLK_n.
Writing a “1” selects the rising edge of the TCLK_n for sam-
pling.
R/W
0
D3
DATAP
DATA Polarity:
Writing a “0” to this bit selects transmit input
and receive output data of all channels to be active “High”.
Writing a “1” selects an active “Low” state.
R/W
0
D2
Reserved
0
D1
GIE
Global Interrupt Enable:
Writing a “1” to this bit globally
enables interrupt generation for all channels.
Writing a “0” disables interrupt generation.
R/W
0
D0
SRESET
Software Reset
μ
P Registers:
Writing a “1” to this bit longer
than 10μs initiates a device reset through the microprocessor
interface. All internal circuits are placed in the reset state with
this bit set to a “1” except the microprocessor register bits.
R/W
0
相關(guān)PDF資料 |
PDF描述 |
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| XRT83L34IV | QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SH314 | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH314_0610 | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH314IB | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH38 | 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83L34_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L34ES | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IV | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IVTR | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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