- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄376463 > XRT83L34 (Exar Corporation) QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PDF資料下載
參數(shù)資料
| 型號(hào)： | XRT83L34 |
| 廠(chǎng)商： | Exar Corporation |
| 英文描述： | QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| 中文描述： | 四T1/E1/J1收發(fā)左/上海收發(fā)器和時(shí)鐘恢復(fù)和抖動(dòng)衰減器 |
| 文件頁(yè)數(shù)： | 29/82頁(yè) |
| 文件大?。?/td> | 447K |
| 代理商： | XRT83L34 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)當(dāng)前第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)
XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
26
TRANSMIT HDB3/B8ZS ENCODER
The Encoder function is available in both
Hardware
and
Host
modes on a per channel basis by controlling the
TNEG_n/CODES_n pin or CODES interface bit. The encoder is only available in single-rail mode. In E1 mode
and with HDB3 encoding selected, any sequence with four or more consecutive zeros in the input serial data
from TPOS_n/TDATA_n, will be removed and replaced with 000V or B00V, where “B” indicates a pulse
conforming with the bipolar rule and “V” representing a pulse violating the rule. An example of HDB3 Encoding
is shown in
Table 3
. In a T1 system, an input data sequence with eight or more consecutive zeros will be
removed and replaced using the B8ZS encoding rule. An example of Bipolar with 8 Zero Substitution (B8ZS)
encoding scheme is shown in
Table 4
. Writing a “
1
” into the CODES_n interface bit or connecting the TNEG_n/
CODES_n pin to a “High” level selects the AMI coding for both E1 or T1 systems.
F
IGURE
12. T
RANSMIT
C
LOCK
AND
I
NPUT
D
ATA
T
IMING
T
ABLE
3: E
XAMPLES
OF
HDB3 E
NCODING
N
UMBER
OF
PULSE
BEFORE
NEXT
4
ZEROS
N
EXT
4
BITS
Input
0000
HDB3 (case1)
odd
000V
HDB3 (case2)
even
B00V
T
ABLE
4: E
XAMPLES
OF
B8ZS E
NCODING
C
ASE
1
P
RECEDING
P
ULSE
N
EXT
8 B
ITS
Input
+
00000000
B8ZS
000VB0VB
AMI Output
+
000+ -0- +
C
ASE
2
Input
-
00000000
B8ZS
000VB0VB
AMI Output
-
000- +0+ -
TCLK
R
TCLK
F
TCLK
TPOS/TDATA
or
TNEG
T
SU
T
HO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT83L34IV | QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SH314 | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH314_0610 | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH314IB | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH38 | 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83L34_05 | 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83L34ES | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT83L34IV | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IV-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT83L34IVTR | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。